Revision 5.01 – November 30, 2005
S5335 – PCI Bus Controller, 3.3V
Data Sheet
The Add-On General Control/Status (AGCSTS) Add-
On Operation Register allows an Add-On CPU to mon-
itor FIFO activity and control FIFO operation. Reset
controls allow the PCI to Add-On FIFO and Add-On to
PCI FIFO flags to be reset (individually). Status bits
indicate if the PCI to Add-On FIFO is empty, has four
or more open spaces, or is full. Status bits also indi-
cate if the Add-On to PCI is empty, has four or more
full spaces or is full. FIFO bus mastering status may
be monitored through this register, but all bus master
configuration is through the MCSR PCI Operation
Register.
3. Define FIFO management scheme. These bits
define what FIFO condition must exist for the PCI
bus request (REQ#) to be asserted by the S5335.
MCSR Bit 13 PCI to Add-On FIFO management
scheme
MCSR
Bit 9
Add-On to PCI FIFO management
scheme
4. Define PCI to Add-On and Add-On to PCI FIFO
priority. These bits determine which FIFO has pri-
ority if both meet the defined condition to request
the PCI bus. If these bits are the same, priority
alternates, with read accesses occurring first.
PCI Initiated FIFO Bus Mastering Setup
For PCI initiated bus mastering, the PCI host sets up
the S5335 to perform bus master transfers. The follow-
ing tasks must be completed to setup FIFO bus
mastering:
MCSR Bit 12 Read vs. write priority
1. Define interrupt capabilities. The PCI to Add-On
and/or Add-On to PCI FIFO can generate a PCI
interrupt to the host when the transfer count
reaches zero.
MCSR
Bit 8
Write vs. read priority
5. Define transfer source/destination address.
These registers are written with the first address
that is to be accessed by the S5335. These
address registers are updated after each access
to indicate the next address to be accessed.
Transfers must start on DWORD boundaries.
INTCSR Bit 15 Enable Interrupt on read transfer
count equal zero
INTCSR Bit 14 Enable Interrupt on write transfer
count equal zero
MWAR
MRAR
All
All
Bus master write address
Bus master read address
2. Reset FIFO flags. This may not be necessary, but
if the state of the FIFO flags is not known, they
should be initialized.
6. Define transfer byte counts. These registers are
written with the number of bytes to be transferred.
The transfer count does not have to be a multiple
of four bytes. These registers are updated after
each transfer to reflect the number of bytes
remaining to be transferred.
MCSR
MCSR
Bit 26
Bit 25
Reset Add-On to PCI FIFO flags
Reset PCI to Add-On FIFO flags
MWTC
MRTC
All
All
Write transfer byte count
Read transfer byte count
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DS1657 137
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
