Revision 5.01 – November 30, 2005
S5335 – PCI Bus Controller, 3.3V
Data Sheet
FIFO PCI Interface (Initiator Mode)
PCI read and write transfers from the S5335 are very
similar. The FIFO management scheme determines
when the S5335 asserts its PCI bus request (REQ#).
When bus grant (GNT#) is returned, the device begins
running PCI cycles. Once the S5335 controls the bus,
the FIFO management scheme is not important. It only
determines when PCI bus control is initially requested.
PCI bus reads and writes are always performed as
bursts by the S5335, if possible.
The S5335 can act as an initiator on the PCI bus. This
allows the device to gain control of the PCI bus to
transfer data to or from the FIFO. Internal address and
transfer count registers control the number of PCI
transfers and the locations of the transfers. The follow-
ing paragraphs assume the proper registers and bits
are programmed to enable bus mastering.
Figure 77. PCI Read from a Full S5335 FIFO
PCI Signals
PCI_CLK
FRAME#
ADDR
DATA
AD[31:0]
IRDY#
TRDY#
DEVSEL#
STOP#
Add-on Signals
WRFULL
FWE
Figure 78. PCI Read from an Empty S5335 FIFO (Target Disconnect)
PCI Signals
PCI_CLK
FRAME#
ADDR
DATA
AD[31:0]
IRDY#
TRDY#
DEVSEL#
STOP#
Target Disconnect with Retry
Add-on Signals
WRFULL
FWE
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AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
