Revision 5.01 – November 30, 2005
S5335 – PCI Bus Controller, 3.3V
Data Sheet
The FRC# and FWC# inputs allow Add-On logic to
reset the PCI to Add-On or Add-On to PCI FIFO flags.
The FIFO flags can always be reset with software
through the Add-On General Control/Status Register
(AGCSTS) or the Bus Master Control/Status Register
(MCSR), but these hardware inputs are useful for
designs which do no implement a CPU on the Add-On
card. Asserting the FRC# input resets the PCI to Add-
On FIFO. Asserting the FWC# input re-sets the Add-
On to PCI FIFO.
The interrupt is posted to the Add-On interface with
the IRQ# output. A high-to-low transition on this output
indicates an interrupt condition. Because there is a
single interrupt output and multiple interrupt condi-
tions, the Add-On Interrupt Control/Status Register
(AINT) must be read to determine the interrupt source.
This register is also used to clear the interrupt, return-
ing IRQ# to its high state. If mailbox interrupts are also
used, this must be considered in the interrupt service
routine.
The AMREN and AMWEN inputs allow Add-On logic
to individually enable and disable bus mastering for
the PCI to Add-On and Add-On to PCI FIFO. These
inputs override the Bus Master Control/Status Register
(MCSR) bus master enable bits. The S5335 may re-
quest the PCI bus for the PCI to Add-On FIFO when
AMREN is asserted and may request the PCI bus for
the Add-On to PCI FIFO when AMWEN is asserted. If
AMREN or AMWEN is deasserted, the S5335
removes its PCI bus request and gives up control of
the bus.
8-Bit and 16-Bit FIFO Add-On Interfaces
The S5335 FIFO may also be used to transfer data
between the PCI bus and 8-bit or 16-bit Add-On inter-
faces. This can be done using FIFO advance
conditions or the S5335 MODE input pin.
The FIFO may be used as an 8-bit or 16-bit wide
FIFO. To use the FIFO as an 8-bit interface, the
advance condition should be set for byte 0 (no data is
transferred in the upper 3 bytes). To use the FIFO as a
16-bit interface, the advance condition should be set
for byte 1 (no data is transferred in the upper 2 bytes).
This allows a simple Add-On bus interface, but it has
the disadvantage of not efficiently utilizing the PCI bus
bandwidth because the host is forced to perform 8-bit
or 16-bit accesses to the FIFO on the PCI bus. This is
the only way to communicate with an 8-bit Add-On
through the FIFO without additional logic to steer byte
lanes on the Add-On data bus. Pass-Thru mode is
more suited to 8-bit Add-On interfaces.
AMREN and AMWEN are useful for Add-Ons with
external FIFOs cascaded into the S5335. For PCI bus
master write operations, the entire S5335 Add-On to
PCI FIFO and the external FIFO may be filled before
enabling bus mastering, providing a single long burst
write rather than numerous short bursts.
In some applications, the amount of data to be trans-
ferred is not known. During read operations, the
S5335, attempting to fill its PCI to Add-On FIFO, may
access up to eight memory locations beyond what is
required by the Add-On before it stops. In this situa-
tion, AMREN can be deasserted to disable PCI reads,
and then FRC# can be asserted to flush the unwanted
data from the FIFO.
Implementing a 16-bit wide FIFO is a reasonable solu-
tion, but to avoid wasting PCI bus bandwidth, the best
method is to allow the PCI bus and the FIFO to oper-
ate with 32-bit data. The S5335 can assemble or
disassemble 32-bit quantities for the Add-On interface.
This is possible through the MODE pin. When MODE
is low, the Add-On data bus is 32-bits. When MODE is
high, the Add-On data bus is 16-bits. When MODE is
configured for 16-bit operation, BE3# becomes ADR1.
FIFO Generated Add-On Interrupts
For Add-On initiated bus mastering, the S5335 may be
configured to generate interrupts to the Add-On inter-
face for the following situations:
With the FIFO direct access signals (RDFIFO# and
WRFIFO#), the MODE pin must reflect the actual Add-
On data bus width. With MODE = 16-bits, the S5335
automatically takes two consecutive, 16-bit Add-On
writes to the FIFO and assembles a 32-bit value. FIFO
reads operate in the same manner. Two consecutive
Add-On reads empty the 32-bit FIFO register. The 16-
bit data bus is internally steered to the lower and upper
words of the 32-bit FIFO register.
- Read transfer count reaches zero
- Write transfer count reaches zero
- An error occurred during the bus master
transaction
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