Revision 5.01 – November 30, 2005
S5335 – PCI Bus Controller, 3.3V
Data Sheet
Table 8. Error Reporting Pins — PCI Local Bus
Signal
Type
Description
PERR#
s/t/s
Parity Error. This pin is used for reporting parity errors during the data portion of a bus transaction for all
cycles except a Special Cycle. It is sourced by the agent receiving data and driven active two clocks fol-
lowing the detection of the error. This signal is driven inactive (high) for one clock cycle prior to returning to
the tri-state condition.
SERR#
o/d
System Error. This pin is used for reporting address parity errors, data parity errors on Special Cycle com-
mands, or any error condition having a catastrophic system impact.
Table 9. Interrupt Pin — PCI Local Bus
Signal Type
Description
INTA#
o/d
Interrupt A. This pin is a level sensitive, low active interrupt to the host. The INTA# interrupt must be used
for any single function device requiring an interrupt capability.
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