Revision 5.01 – November 30, 2005
S5335 – PCI Bus Controller, 3.3V
Data Sheet
Figure 5. FIFO PCI Bus Mastering Operation Diagram
S5335
B0
B0
B0
B1
B2
B3
B0
B1
B2
B3
B0
B1
B2
B3
B0
B1
B2
B3
B0
B1
B2
B3
B0
B1
B2
B3
B1
B1
B2
B3
Endian
Converter
B2
B3
B0
B1
B2
B3
B0
B1
B2
B3
B0
B1
B2
B3
B0
B1
B2
B3
B0
B1
B2
B3
B0
B1
B2
B3
B0
B1
B2
B3
B0
B1
B2
B3
Endian
Converter
32-Bit Master Write Address Register
32-Bit Master ReadAddress Register
30-Bit Master Read Count Register
28-Bit Master Write Count Register
AMCC Confidential and Proprietary
DS1657 18