Revision 5.01 – November 30, 2005
S5335 – PCI Bus Controller, 3.3V
Data Sheet
Table 14. Pass-Thru Interface Pins (Continued)
Signal
Type
Description
PTBE[3:0]#
out
Pass-Thru Byte Enables. These signals indicate which bytes are requested for a given Pass-Thru
operation. They are valid during the presence of signal PTATN# active.
PTADR#
PTWR
in
Pass-Thru Address. This signal causes the actual Pass-Thru requested address to be presented as
outputs on the DQ pins DQ[31:0] for Add-Ons with 32-bit buses, or the low-order 16 bits for Add-Ons
with 16-bit buses. It is necessary that all other bus control signals be in their inactive state during the
assertion of PTADR#. The purpose of this signal is to provide the direct addressing of external Add-
On peripherals through use of the PTNUM[1:0] and the low-order address bits presented on the DQ
bus with this pin active.
out
Pass-Thru Write. This signal identifies whether a Pass-Thru operation is a read or write cycle. This
signal is valid only when PTATN# is active.
Table 15. System Pins
Signal
Type
Description
SYSRST#
out
System Reset. This low active output is a buffered form of the PCI bus reset, RST#. It is not synchro-
nized to any clock within the PCI interface controller. Additionally, this signal can be invoked through
software from the PCI host interface.
BPCLK
IRQ#
out
out
in
Buffered PCI Clock. This output is a buffered form of the PCI bus clock and, as such, has all of the
behavioral characteristics of the PCI clock (i.e., DC-to-33 MHz capability).
Interrupt. This pin is used to signal the Add-On system that a significant event has occurred as a result
of activity within the PCI controller.
RSVD
Reserved. This pin must be left open at all times.
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