Revision 5.01 – November 30, 2005
S5335 – PCI Bus Controller, 3.3V
Data Sheet
Synchronous WR# FIFO Timing
Table 69. Synchronous WR# FIFO Timing
Functional Operation Range (V = 3.3V ±5%, 0°C to 70°C, 50 pf load on outputs)
CC
Symbol
t113
Parameter
SELECT# Setup to BPCLK Rising Edge
SELECT# Hold from BPCLK Rising Edge
ADR[6:2] Setup to BPCLK Rising Edge
ADR[6:2] Hold from BPCLK Rising Edge
BE[3:0]# Setup to BPCLK Rising Edge
BE[3:0]# Hold from BPCLK Rising Edge
DQ[31:0] Setup to BPCLK Rising Edge
DQ[31:0] Hold from BPCLK Rising Edge
WR# Setup to BPCLK Rising Edge
Min
15
0
Max
Units
ns
Notes
-
-
t113a
t117
ns
15
0
-
ns
t117a
t121
-
ns
15
0
-
ns
t121a
t123
-
ns
15
0
-
ns
t123a
t122
-
ns
15
0
-
ns
t122a
t159
WR# Hold from BPCLK Rising Edge
WRFULL Status Valid to BPCLK Rising Edge
FWE Status Valid to BPCLK Rising Edge
-
ns
-
15
15
ns
t160
-
ns
Figure 105. Synchronous WR# FIFO Timing
BPCLK
t113
SELECT#
ADR[6:2]
BE[3:0]#
DQ[31:0]
t117
t121
t123
t123a
t122
WR#
WRFULL
FWE
t159
3ns
t160
4ns
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