Revision 5.01 – November 30, 2005
S5335 – PCI Bus Controller, 3.3V
Data Sheet
Figure 109. Pass-Thru Status Indicator Timing
BPCLK
PTATN#
PTWR
Valid
Valid
PTBURST#
PTNUM[1:0]
t
24
PTBE[3:0]#
t
25
Target Byte-Wide nv Memory Interface Timing
Table 71. Target Byte-Wide Memory Interface Timing
Functional Operation Range (V =3.3V ±5%, 0°C to 70°C, 50 pF load on outputs)
CC
Symbol
Parameter
Min
Max
Units
Notes
Note 1
t
t
t
t
t
t
t
t
t
t
t
ERD# Cycle Time
ERD# Low Time
ERD# High Time
8T
-
ns
35
6T
2T
T
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
36
37
38
39
40
41
43
44
45
46
EA[15:0] Setup to ERD# or EWR# Low
EA[15:0] Hold from ERD# or EWR# High
EQ[7:0] Setup to ERD# Rising Edge
EQ[7:0] Hold from ERD# Rising Edge
EWR# Low Time
T
10
2
6T
2T
0
EWR# High Time
EQ[7:0] Setup to EWR# Low -10
EQ[7:0] Hold from EWR# High
T
Notes:
1. T represents the clock period for the PCI bus clock (30ns @ 33 MHz).
2. The write cycle time is controlled by both the PCI bus clock and software operations to initiate the write operation of nv memory. This param-
eter is the result of several software operations to the Bus Master Control/Status Register (MCSR).
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