Revision 5.01 – November 30, 2005
S5335 – PCI Bus Controller, 3.3V
Data Sheet
Asynchronous WR# Register Access Timing
Table 67. Asynchronous WR# Register Access Timing
Functional Operation Range (V = 3.3V ±5%, 0°C to 70°C, 50 pf load on outputs)
CC
Symbol
Parameter
Min
Max
Units
Notes
t
t
t
t
t
t
t
t
t
t
t
SELECT# Setup to WR# Rising Edge
8
-
ns
111
SELECT# Hold from WR# Rising Edge
ADR[6:2] Setup to WR# Rising Edge
ADR[6:2] Hold from WR# Rising Edge
BE[3:0]# Setup to WR# Rising Edge
BE[3:0]# Hold from WR# Rising Edge
WR# Low Time
0
8
0
8
0
4
5
3
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
111a
115
-
115a
119
-
-
119a
132
-
DQ[31:0] Setup to WR# Rising Edge
DQ[31:0] Hold from WR# Rising Edge
WRFULL Status Valid from WR# Rising Edge
FWE Status Valid from WR# Rising Edge
-
134
-
134a
154
27
40
-
155
Note: For non-burst FIFO read/write operations
Figure 102. Asynchronous WR# FIFO Timing
t111
SELECT#
ADR[6:2]
t115
t119
BE[3:0]#
DQ[31:0]
WR#
t134a
t134
t132
t154
13ns
WRFULL
FWE
t155
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