Part Number S3091
Revision A – February 22, 2002
S3091
SONET/SDH/ATM OC-192 16:1 Transmitter
FEATURES
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Silicon Germanium BiCMOS technology
Complies with Telcordia, ITU-T, and G.709
specifications
On-chip high-frequency PLL for clock generation
OC-192 with FEC and Digital Wrapper (DW)
(9.953 to 10.709 Gbps)
Reference frequency of 155.52 or 622.08 MHz
(or equivalent FEC or DW rate)
16-bit parallel, 622.08 Mbps LVDS data path
Lock detect/Phase error indicator
Low jitter CML differential or single-ended
serial interface
Dual +3.3 V and -5.2 V power supply
Supports line timing
Internal FIFO to decouple transmit clocks
311.04 MHz or 622.08 MHz parallel input clock
Programmable skew on 311.04 MHz parallel
clock mode
148-pin CBGA package
Typical power dissipation 2.3 W
DEVICE SPECIFICATION
APPLICATIONS
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SONET/SDH-based transmission systems
SONET/SDH modules
SONET/SDH test equipment
ATM over SONET/SDH
Section repeaters
Add Drop Multiplexers (ADM)
Broad-band cross-connects
Fiber optic terminators
Fiber optic test equipment
GENERAL DESCRIPTION
The S3091 SONET/SDH MUX chip is a fully inte-
grated serializer with SONET OC-192 with FEC and
Digital Wrapper (9.953 to 10.709 Gbps) rate capabil-
ity. The chip performs all necessary parallel-to-serial
functions in conformance with SONET/SDH/Digital
Wrapper transmission standards. The device is suit-
able for SONET-based ATM applications. Figure 1
shows a typical network application.
On-chip clock synthesis PLL components are con-
tained in the S3091 MUX chip, allowing the use of a
slower external transmit clock reference. The chip can
be used with a 155.52 or 622.08 MHz reference clock
(or equivalent FEC or DW rate), in support of existing
system clocking schemes.
Figure 1. System Block Diagram
INDUS
(19201),
GANGES
(19202)
or
HUDSON
(19203)
16
S3091
OTX
ORX
S3092
16
16
S3092
ORX
OTX
S3091
16
INDUS
(19201),
GANGES
(19202)
or
HUDSON
(19203)
1
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
