S3091 – SONET/SDH/ATM OC-192 16:1
Transmitter
Parallel-to-Serial Converter
The parallel-to-serial converter shown in Figure 4 is
comprised of two byte-wide registers. The PICLK
(622.08 MHz or 311.04 MHz dual edge clock) clocks in
the data from the PINP/N[15:0] bus to the first register
of the parallel-to-serial register. The second register is
a parallel loadable shift register, which takes its paral-
lel input from the first register.
An internally generated byte clock activates the paral-
lel data transfer between registers. The serial data is
shifted out of the second register.
If the 311.04 MHz dual edge PICLK mode is selected,
PICLK skew relative to PINP/N[15:0] may be intro-
duced to optimize data and clock setup and hold
times. SKEWSEL[1:0] may be used to control the
skew which is nominally 815 ps. See Table 5 for skew
selections.
FIFO
A FIFO is added to decouple the internal and external
parallel clocks. The internally generated divide-by-16
clock is used to clock out data from the FIFO. PHINIT
and LOCKERRB are used to center or reset the FIFO.
The PHINIT and LOCKERRB signals will center the
FIFO after the third PICLK pulse. (See Figure 9.) This
ensures that PICLK is stable. This scheme allows the
user to have an infinite PCLK to PICLK delay through
the ASIC. Once the FIFO is centered, the PCLK to
PICLK delay can have a maximum drift as specified in
Table 20.
FIFO Initialization
The FIFO can be initialized in one of the following
three ways:
1. During power up, once the PLL has locked to the
reference clock provided on the REFCLK pins,
the LOCKERRB will go active and initialize the
FIFO.
2. When RSTB goes active, the entire chip is reset.
This causes the PLL to go out of lock, and thus
the LOCKERRB goes inactive. When the PLL
reacquires the lock, the LOCKERRB goes active
and initializes the FIFO. Note that PCLK does not
toggle when RSTB is active.
3. The user can also initialize the FIFO by raising
PHINIT.
During normal running operation, the incoming data is
passed from the PICLK timing domain to the internally
generated divide-by-16 clock timing domain. Although
the frequency of PICLK and the internally generated
clock is the same, their phase relationship is arbitrary.
Revision A – February 22, 2002
DEVICE SPECIFICATION
Table 3. Reference Frequency
REFSEL
0
1
REFCLK
155.52 MHz (or equivalent FEC or DW rate)
622.08 MHz (or equivalent FEC or DW rate)
To prevent errors caused by short setup or hold times
between the two timing domains, the timing generator
circuitry monitors the phase relationship between
PICLK and the internally generated clock. When a
potential setup or hold time violation is detected,
Phase Error (PHERR) goes High. If the condition per-
si sts, PHERR will r em ai n Hi gh. W hen PHERR
conditions occur, PHINIT should be activated to
recenter the FIFO (at least 10 ns). This can be done
by connecting PHERR to PHINIT. When realignment
occurs, four to ten bytes of data will be lost. The user
can also take in the PHERR signal, process it, and
send an output to PHINIT in such a way that idle bytes
are lost during the realignment process. PHERR will
go inactive when the realignment is complete. (See
Figure 9,
Phase Adjust Timing.)
Power Sequencing
In order to avoid latchup, it is required that the -5.2 V
power be applied to the S3091 for a minimum of 50 ms
before 3.3 V power is applied.
Table 4. Clock Select
CLKSEL
0
1
PICLK Frequency
622.08 MHz (or equivalent FEC or DW rate)
311.04 MHz (or equivalent FEC or DW rate)
Table 5. Skew Select
SKEWSEL[1]
0
0
1
1
SKEWSEL[0]
0
1
0
1
311 PICLK Target
Skew
915 ps
1015 ps
715 ps
815 ps
8
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
