S3091 – SONET/SDH/ATM OC-192 16:1
Transmitter
Table 6. Input Pin Assignment and Descriptions
Pin Name
Level
I/O
Pin #
Revision A – February 22, 2002
DEVICE SPECIFICATION
Description
PINP0
PINN0
PINP1
PINN1
PINP2
PINN2
PINP3
PINN3
PINP4
PINN4
PINP5
PINN5
PINP6
PINN6
PINP7
PINN7
PINP8
PINN8
PINP9
PINN9
PINP10
PINN10
PINP11
PINN11
PINP12
PINN12
PINP13
PINN13
PINP14
PINN14
PINP15
PINN15
PICLKP
PICLKN
LVDS
I
N2
N3
P3
P4
N4
N5
P5
P6
N6
N7
P7
P8
N8
N9
P9
P10
M11
M12
N12
N13
N14
M14
L13
K13
K14
J14
H14
G14
G13
F13
F14
E14
D14
C14
Parallel Data Input.
A 16-bit parallel, 622.08 Mbps, aligned to the
PICLK parallel input clock. PINP/N[15] is the most significant bit (corre-
sponding to bit 1 of each word, the first bit transmitted). PINP/N[0] is
the least significant bit (corresponding to bit 16 of each word, the last
bit transmitted). PINP/N[15:0] is sampled on the rising edge of PICLK
(when CLKSEL = 0) or on the rising and falling edge of PICLK (when
CLKSEL = 1). Internally biased and terminated.
LVDS
I
Parallel Input Clock.
A 622.08 MHz or dual edge 311.04 MHz nomi-
nally 50% duty cycle input clock, to which PINP/N[15:0] is aligned.
PICLK is used to transfer the data on the PIN inputs into a holding reg-
ister in the parallel-to-serial converter. Internally biased and termi-
nated.
Test Clock Enable.
Active Low. Set Low to provide access to the PLL
during production tests. (Pull High for normal operation.)
Reference Clock.
Input used as the reference for the internal bit clock
frequency synthesizer. Internally terminated and biased.
Master Reset.
Active Low. Reset input for the device. For correct
reset, this input must be asserted Low for 100 ns. During reset, PCLK
does not toggle.
Loop Filter Capacitors.
Connections for external loop filter capacitor
and resistors. (See Figure 15.)
TESTB
REFCLKP
REFCLKN
RSTB
LVTTL
Diff.
ECL
LVTTL
I
I
I
C6
B1
C1
A7
CAP1
CAP2
Analog
I
B4
C4
9
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
