S3038
SONET/SDH/ATM OC-12 QUAD TRANSCEIVER
Table 18. Receiver Timing (See Figure 13)
Symbol
Description
POCLK Duty Cycle
Min
Max Units
Comments
40
60
3
%
ns
ns
ns
ns
POCLK Rise/Fall Time
tSPOUT
Data Setup w.r.t. POCLK
Data Hold Time w.r.t. POCLK
POCLK Low to POUTx[7:0] valid
3
3
tHPOUT
tPPOUT
-2
2
1. All AC measurements are made from the reference level of the clock 1.4V to the valid input or output data level (0.8 or 2V).
Figure 13. Receiver Output Timing Diagram
Duty Cycle MAX
1.4V
Duty Cycle MIN
POCLK
tS
tH
POUT
tP
POUT
POUT
2V
0.8V
POUT[7:0]
Notes on Output Timing:
1. Output propagation delay time of LVTTL outputs is the time in nanoseconds from the 1.4V point of the
reference signal to the valid input or output data level (0.8V or 2V).
2. Maximum output propagation delays of LVTTL outputs are measured with a 10 pF load on the outputs.
3. Output propagation delay time of high speed LVPECL outputs is the time in nano seconds from the
cross-over point of the reference signal to the cross-over point of the output.
Table 19. PCLK Timing
Symbol
tDPCLK
tDPCLK
Description
Min
2
Max Units
Comments
CLKSEL = 0
Delay from REFCLK to PCLK
Delay from REFCLK to PCLK
7.5
7.5
ns
ns
2
CLKSEL = 1
Figure 14. PCLK Timing (See Table 19)
REFCLK
PCLK
tD
PCLK
24
September 16, 1999 / Revision B
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
