S3017/S3018
SONET/SDH/ATM OC-12 TRANSMITTER AND RECEIVER
S3017 Pin Assignment and Descriptions
Pin Name
Level I/O
Pin # Description
PIN7
PIN6
PIN5
PIN4
PIN3
PIN2
PIN1
PIN0
TTL
I
33
31
30
29
23
22
20
19
Parallel data input, a 77.76 Mbyte/sec word, aligned to the
PICLK parallel input clock. PIN7 is the most significant bit
(corresponding to the first bit transmitted). PIN0 is the least
significant bit (corresponding to the last bit transmitted). PIN(7-0)
is sampled on the rising edge of PICLK.
PICLK
TTL
TTL
I
I
12
Parallel input clock, a 77.76 MHz nominally 50% duty cycle input
clock, to which PIN(7-0) is aligned. PICLK is used to transfer the
data on the PIN inputs into a holding register in the parallel-to-
serial converter. The rising edge of PICLK samples PIN(7-0).
TESTCLKEN
4
Test clock enable signal, active high to enable the reference
clock to be used in place of the VCO for testing. Allows a means
of testing the functions of the chip without the use of the PLL.
Set low for normal operation.
REFCKINP
REFCKINN
Diff.
I
I
49
48
Reference clock input used as the reference for the internal bit
clock frequency synthesizer.
PECL
LOCLPEN
TTL
8
Local loopback enables the LPDATO output when low and
TSCLKSEL is low. When LOCLPEN is high, the LPDATO output
is held in the inactive state to prevent interference between the
transmit and receive devices.
RSTB
TTL
TTL
TTL
TTL
–
I
I
9
35
11
7
Reset input for the device, active low. During reset, PCLK does
not toggle.
TSCLKSEL
TESTRST
REFSEL
Active high transmit clock select input which, when enabled,
directs the transmit serial clock through the LPDATOP/N output.
I
Test reset, used to reset portions of the clock recovery PLL
during production testing. Held low for normal operation.
I
Reference select, used to select the reference clock frequency.
Set low to select 77.76 MHz. Set high to select 19.44 MHz for
applications less demanding than SONET/SDH.
CAP1
CAP2
I
1
52
The loop filter capacitor is connected to these pins. The
capacitor value should be 0.01µf ±10% tolerance, X7R dielectric.
50 V is recommended (16 V is acceptable).
SERDATOP
SERDATON
Diff.
PECL
O
47
45
High-speed, source-terminated differential PECL. Serial output
data stream signals, normally connected to an optical transmitter
module.
8
December 10, 1999 / Revision B
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
