SONET/SDH/ATM OC-12 TRANSMITTER AND RECEIVER
S3017/S3018
S3017 Pin Assignment and Descriptions (Continued)
Pin Name
Level I/O
Pin # Description
LPDATOP
LPDATON
Diff.
PECL
O
44
43
Loopback serial data stream signals, normally connected to a
companion S3018 device for diagnostic loopback purposes.
They are held inactive when LOCLPEN is high and TSCLKSEL
is low. The serial data stream is output when LOCLPEN is low
and TSCLKSEL is low. When enabled by the TSCLKSEL input,
the transmit serial clock will be output through this pin. The
transmit serial clock is a buffered version of the internal
frequency synthesizer clock, which is phase-aligned with the
SERDATO output signal. The SERDATO is updated on the
falling edge of the transmit serial clock.
PCLK
TTL
0V
O
16
Parallel reference clock generated by dividing the internal bit
clock by eight. It is normally used to coordinate byte-wide
transfers between upstream logic and the S3017 device.
AVEE
–
2, 39, 41, Analog 0V
42, 51
AVCC
+5V
+5V
0V
–
–
–
3, 38, 40, Analog +5V
46, 50
ECLVCC
ECLVEE
5, 15, 25, Digital +5V
28, 37
6, 10, 18, Digital 0V
21, 32, 36
TTLGND
TTLVCC
NC
0V
+5V
–
–
–
–
13, 17, 27 Digital 0V
14, 24, 26 Digital +5V
34
No Connection
9
December 10, 1999 / Revision B
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
