S3017/S3018
SONET/SDH/ATM OC-12 TRANSMITTER AND RECEIVER
S3018 Pin Assignment and Descriptions
Pin Name
Level I/O
Pin # Description
SERDATIP
SERDATIN
Diff.
PECL
I
45
46
Serial data stream signals normally connected to an optical
receiver module. A clock is recovered from transitions on the
SERDATI inputs.
LPDATIP
LPDATIN
Diff.
PECL
I
42
44
Serial data stream signal, normally connected to a companion
S3017 device for diagnostic loopback purposes. Clock is
recovered from transitions on the LPDATI inputs while in
diagnostic loopback.
LOCLPEN
TSTCLKEN
OOF
TTL
TTL
TTL
I
I
I
8
4
Selects diagnostic loopback. When LOCLPEN is high, the
S3018 device uses the primary data (SERDATI) input. When
low, the S3018 device uses the diagnostic loopback data
(LPDATI) input.
Test clock enable signal, set high to enable the reference clock
to be used in place of the VCO for testing. Allows a means of
testing the functions of the chip without the use of the PLL. Set
low for normal operation.
31
Out of frame indicator used to enable framing pattern detection
logic in the S3018. This logic is enabled by a rising edge on
OOF, and remains enabled until frame boundary is detected or
when OOF is set low, whichever is longer. OOF is an
asynchronous signal with a minimum pulse width of one POCLK
period. (See Figures 13 and 14.)
LOS
PECL
I
34
An active-high, single-ended 10K ECL input to be driven by the
external optical receiver module to indicate a loss of received
optical power. When LOS is high, the data on the Serial Data In
(SERDATIP/N) pins will be internally forced to a constant zero,
LOCKDET will be forced low, and the PLL will lock to the
REFCKINP/N inputs. This signal must be used to assure correct
automatic reacquisition to serial data following an interruption
and subsequent reconnection of the optical path. (This ensures
that the PLL does not "wander" out of reacquisition range by
tracking the random phase/frequency content of the optical
detector's noise floor while monitoring "dark" fiber.) When LOS
is low, data on the SERDATIP/N pins will be processed
normally.
REFCKINP
REFCKINN
Diff.
I
I
49
48
Input normally used as the reference for the integral clock
recovery PLL.
PECL
RSTB
TTL
33
Master reset input for the device, active low. Initializes the
device to a known state and forces the PLL to acquire to the
reference clock. A reset of at least 16 ms should be applied at
power-up and whenever the user wishes to force the PLL to re-
acquire to the reference clock. The S3018 will also re-acquire to
the reference clock if the serial data input is held quiescent for at
least 16 ms.
10
December 10, 1999 / Revision B
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
