S3017/S3018
SONET/SDH/ATM OC-12 TRANSMITTER AND RECEIVER
S3017 TRANSMITTER
FUNCTIONAL DESIGN
The REFCKINP/N input must be generated from a
differential PECL crystal oscillator which has a fre-
quency accuracy of better than 20 ppm in order for the
TSCLK frequency to have the same accuracy required
for operation in a SONET system. Lower accuracy
crystal oscillators may be used in applications less
demanding than SONET/SDH.
The S3017 transmitter chip performs the serializing stage
intheprocessingofatransmitSONETSTS-12bitserial
data stream. It converts the byte serial 77.76 Mbyte/sec
data stream to bit serial format at 622.08 Mbit/sec.
A high-frequency bit clock can be generated from a
77.76 MHz frequency reference by using an integral
frequency synthesizer consisting of a phase-locked
loop circuit with a divider in the loop.
The on-chip PLL consists of a phase detector, which
compares the phase relationship between the VCO out-
putandtheREFCKINP/Ninput,aloopfilterwhichconverts
the phase detector output into a smooth DC voltage,
and a VCO, whose frequency is varied by this voltage.
Diagnosticloopbackisprovided(transmittertoreceiver)
when used with the compatible S3018. (See Other
Operating Modes.)
The loop filter generates a VCO control voltage based
on the average DC level of the phase discriminator
output pulses. A single external clean-up capacitor is
utilized as part of the loop filter. The loop filter’s corner
frequency is optimized to minimize output phase jitter.
Clock Synthesizer
The Clock Synthesizer, shown in the block diagram in
Figure 4, is a monolithic PLL that generates the serial
output clock phase synchronized with the input refer-
ence clock (REFCKINP/N).
Figure 5. S3018 Receiver
LOS
8
1:8 SERIAL
POUT[7:0]
TO PARALLEL
TIMING
POCLK
OOF
GEN
FRAME
BYTE
DETECT
FP
LOCLPEN
2
2
M
U
X
SERDATIP/N
LPDATIP/N
BACKUP
REFERENCE
GEN
CLOCK
RECOVERY
LOCKDET
REFSEL
2
REFCKINP/N
CAP1
CAP2
TSTCLKEN
RSTB
4
December 10, 1999 / Revision B
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
