E4/STM-1/OC-3 ATM INTERFACE CIRCUITS
S3015/S3016
CMI Decoding
Serial Clock Output to Data Output Timing
The CMI decoder block on the S3016 accepts serial
data from the SERDATIP/N input at the rate of 139.264
or 155.52 Mb/s. The incoming CMI data, which has
transitions that represent this data rate (the clock asso-
ciated with this data would be running at twice this rate),
is then decoded from CMI to NRZ format.
The serial data is clocked out on the falling edge of
SERCLKOP. (See Figure 12.) This timing is valid in
both NRZ and CMI modes.
Input Jitter Tolerance
Input jitter tolerance is defined as the peak to peak
amplitude of sinusoidal jitter applied on the input signal
that causes an equivalent 1 dB optical/electrical power
penalty. OC-3 and E-4 input jitter tolerance require-
ments are shown in Figure 13.
Loss of Signal
The clock recovery circuit monitors the incoming data
stream for loss of signal. If the incoming encoded data
streamhashadnotransitionscontinuouslyfor96to224
recovered clock cycles, loss of signal is declared and
the PLL will switch from locking onto the incoming data
tolockingontothereferenceclockpertherequirements
of G.775. Alternatively, the loss-of signal (LOSIN) input
can force a loss-of-signal condition. This signal is com-
pared internally against the LOSREF input reference
voltage. This input can be set to meet the conditions
showninFigure11. Ifthezerotopeaksignalleveldrops
below the LOSREF/20 voltage level for more than 96 to
224 bit intervals, a loss of signal condition will be
indicated on the LOSOUT pin and the PLL will change
itsreferencefromtheserialdatastreamtothereference
clock. When the peak input voltage is greater than
LOSREF/10, the loss of signal condition will be
deasserted and the PLL will recover the clock from the
serial data inputs.
The S3016 PLL complies with the minimum jitter toler-
ance for clock recovery proposed for SONET/SDH
equipment defined by the Bellcore TA-NWT-000253
standard when used as shown in Figure 13. The S3016
PLL also complies with the minimum jitter tolerance for
clock recovery as defined in the ITU-T E4 specification
when used as shown in Figure 17.
Figure 12. S3016 Clock to Data Timing
SERCLKOP
SERDATOP/N
tP
SER
InNRZmode, alogiclowlevelontheLOSOPTinputwill
cause the PLL to change its reference to the reference
clock. This pin should be driven by a PECL compatible
level signal detect signal from the fiber optic receiver.
Figure 13. Clock Recovery Jitter Tolerance
Compliant to G.823 and G.825
Figure 11. Criteria for determination of transition
conditions. Compliant to G.775.
nominal value
maximum
Sinusoidal
Input Jitter
Amplitude
(UI p-p)
A2
A3
A4
cable loss
3 dB
“transition condition”
must be declared
17
35
Tolerance range
f9
f0 f1
f2 f3
f4
f4
“no transition condition” or “transition
condition” may be declared
f9
(Hz)
f2
A3 A4
f0
f1
f3
A2
“no transition condition”
must be declared
(KHz)
(Hz) (Hz)
(KHz) (MHz)
Level below Nominal
OC-3
10
6.5
6.5
1.5 .15
1.5 0.15
1.5 0.075
30 300
65
65
65
—
15
391
391
The signal level 17 is (maximum cable loss +3)
dB below nominal.
STM-1 (Optical) 0.125
STM-1 (Electrical) 0.125
19.3 500
19.3 500
1.3
1.3
3.25
The signal level 35 is greater than the maximum
expected cross-talk level.
E4
TBD
0.5
1.5 0.075
TBD 200
65
1.3
15
Note:
1. Only tested to 20 due to test equipment limitation.
7
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
