E4/STM-1/OC-3 ATM INTERFACE CIRCUITS
S3015/S3016
S3016 Pin Assignment and Descriptions
Pin Name
Level I/O
Pin # Description
BUFINA
BUFINB
Analog
Analog
TTL
I
I
22
23
Buffer inputs to the equalizer network buffer circuit. This circuit
provides a high impedance load to the transformer termination
network in order to comply with the required return loss
specifications. These pins should be connected as shown in
Figure 17. These pins are electrically equivalent.
ANDATIN
16
Analog serial data input from the equalizer circuit. It must be
connected to the output of the equalizer circuit as shown in
Figure 17. When the S3016 is used with a fiber optic receiver,
this input should be left open and the SERDATIP/N inputs
should be used.
EQUALSEL
REFCKIN
I
I
I
I
I
I
33
10
Equalization select used to select SERDATIP/N or ANDATIN. A
logic high selects ANDATIN.
Single-
ended
TTL
Input used as the reference for the VCO when the input data
signal is lost.
SERDATIP
SERDATIN
Diff.
PECL
45
46
Serial data in. Clock is recovered from transitions on these
inputs when selected by EQUALSEL.
TSTCLKEN
CMISEL
RSTB
TTL
TTL
TTL
35
32
34
Test clock enable signal, active high, that enables the reference
clock to be used in place of the VCO for testing. Allows a means
of testing the functions of the chip without the use of the PLL.
CMI Select used to select CMI or NRZ. A logic high selects CMI
mode. Either ANDATIN or SERDATIN may be used as inputs to
the CMI decoder.
Reset input for the device, active low. Initializes the device to a
known state, shuts off SERCLKOP/N, and forces the PLL to
acquire to the reference clock. A reset of at least 16 ms should
be applied at power-up and whenever it is necessary to
reacquire to the reference clock. The S3016 will also reacquire
to the reference clock if the serial data is held quiescent
(constant ones or constant zeros) or LOSIN or LOSOPT are
activated for at least 224 bit intervals.
11