S3015/S3016
E4/STM-1/OC-3 ATM INTERFACE CIRCUITS
CMI Encoding
Figure 5. CMI Encoded Data
Coded Mark Inversion format (CMI) ensures at least
one data transition per 1.5 bit periods, thus aiding
the clock recovery process. Zeros are represented
by a Low state for one half a bit period, followed by
a High state for the rest of that bit period. Ones are
represented by a steady Low or High state for a full
bit period. The state of the ones bit period alternates
at each occurrence of a one. Figure 5 shows an
example of CMI-encoded data. The STS-3 electrical
interface and the E4 interface are specified to have
CMI-encoded data.
Figure 6. Jitter Generation Specifications
Compliant to G.823 and G.825
The CMI encoder on the S3015 accepts serial data
from SERDATIP/N at 139.264 or 155.52 Mb/s. The
data is then encoded into CMI format, and the result
is shifted out with transitions at twice the basic data
rate. The CMISEL input controls whether the CMI en-
coder is in the data path. A CMI code violation can be
inserted for diagnostic purposes by activating the
DLCV input. The DLCV input is sampled on every
cycle of the serial clock to allow a single or multiple
line code violations to be inserted. This violation is
either an inverted zero code or an inversion of the
alternating ones logic level, depending on the state of
the data. Subsequent one codes take into account
the induced violation to avoid error multiplication.
A1
A2
f1
f2
f3
f1(Hz)
—
A2
f2(KHz) f3(MHz) A1
.01(1)
.15(2)
.075(2)
—
65
10
—
.01(1)
1.5(2)
1.5(2)
OC-3
STM-1 500
1.3
3.5
E4
200
1. UI rms
2. UI p–p
Jitter Generation
Jitter Generation is defined as the amount of jitter at the
OC-3 or E-4 output of equipment. Jitter generation for
OC-3 shall not exceed 0.01 UI rms when measured
using a highpass filter with a 12 kHz cutoff frequency.
Figure 7. S3015 Maximum Allowable Input Jitter
A1
ForSTM-1andE4, thejittergeneratedshallnotexceed
the specifications shown in Figure 6.
Slope = +20 dB/decade
In order to meet the SONET, STM-1 E4 jitter specifica-
tionsasshowninFigure6,theSERDATIP/Nserialdata
input must meet the jitter characteristics as shown in
Figure 7.
A2
500Hz
OC-3
f2
225 KHz 1.3 MHz
f2(KHz)
—
A1
A2
.005(1) .005(1)
1.45(2) .10(2)
1.45(2) .025(2)
STM-1 65
E4
10
1. UI rms
2. UI p–p
4
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
