S3015/S3016
E4/STM-1/OC-3 ATM INTERFACE CIRCUITS
trolled Oscillator (VCO), which generates the recov-
ered clock. Frequency stability without incoming data
is guaranteed by an alternate reference input
(REFCKIN) to which the PLL locks when data is lost.
S3016 RECEIVER FUNCTIONAL
DESCRIPTION
The S3016 receiver provides the first stage of digital
processing of a receive SONET STS-3 or ITU-T E4 serial
bit stream. A Coded Mark Inversion (CMI) decoder can
be enabled for decoding STS-3 electrical and E4 signals.
When the test clock enable (TSTCLKEN) input is set
high, the clock recovery block is disabled. The refer-
ence clock (REFCKIN) is used as the bit rate clock
input in place of the recovered clock. This feature is
used for functional testing of the device.
Clock recovery is performed on the incoming
scrambled NRZ or CMI–coded data stream. A reference
clock is required for phase locked loop start-up and
proper operation under loss of signal conditions. An
integral prescaler and phase locked loop circuit is used
to multiply this reference frequency to the nominal bit rate.
The loop filter transfer function is optimized to enable
the PLL to track the jitter, yet tolerate the minimum
transition density expected in a received SONET or
E4 data signal. This transfer function yields a typical
capture time of 16 µs for random incoming NRZ data.
Clock Recovery
The total loop dynamics of the clock recovery PLL yield
a jitter tolerance which exceeds the minimum tolerance
proposed for OC-3/STM-1/E4 equipment by the Bellcore
and ITU-T documents, shown in Figure 13.
The Clock Recovery function, as shown in the block
diagram in Figure 10, generates a clock that is fre-
quency matched to the incoming data baud rate at
the SERDATIP/N differential inputs. The clock is
phase aligned by a PLL so that it samples the data
in the center of the data eye pattern.
Optical and Electrical Interfaces
The digital data inputs (SERDATIP/N) are the PECL
inputs from an optical to electrical converter, as shown
in Figure 16. The data input for the coaxial interface is
ANDATIN, which is the serial data input from the equal-
izer circuit and should be connected as shown in Figure
17. The EQUALSEL input is used to select either
SERDATIP/N or ANDATIN.
The phase relationship between the edge transitions
of the data and those of the generated clock are
compared by a phase/frequency discriminator. Output
pulses from the discriminator indicate the required
direction of phase corrections. These pulses are
smoothed by an integral loop filter. The output of the
loop filter controls the frequency of the Voltage Con-
Figure 10. S3016 OC-3/STM-1/E4 Receiver Functional Block Diagram
CAP1
LOOP
VCO
FILTER
CAP2
REFCKIN
TSTCLKEN
CMISEL
REFCKOUT
2
SERCLKOP/N
LCV
CLOCK
DIVIDER
C
M
I
LOCK
LOSOUT
DETECTOR
RSTB
2
BUFINA, BUFINB
BUFOUT
PHASE DETECTOR
2
SERDATOP/N
LOSOPT
2:1
MUX
LOSIN
LOSREF
2
SERDATIP/N
2:1
MUX
ANDATIN
EQUALSEL
6
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
