S3014
SONET/SDH CLOCK RECOVERY AND SYNTHESIS UNIT
Pin Assignment and Descriptions (Continued)
Pin Name
Level I/O
Pin # Description
SERDATOP
SERDATON
Diff.
ECL
O
20
21
Serial data out signal. In the Clock Recovery mode, this signal is
the delayed version of the incoming data stream (SERDATI)
updated on the falling edge of Serial Clock Out (SERCLKOP).
SERCLKOP
SERCLKON
Diff.
ECL
O
15
14
Serial clock out signal that is phase aligned with Serial Data Out
(SERDATO) when Lock Detect (LOCKDET) is high. When Lock
Detect is low, the signal is synchronous with Reference Clock
(REFCKINP/N).
REFCKOUT
AVEE
TTL
O
31
Single-ended TTL reference clock output. See Table 1.
Analog power (-5.2V)
-5.2V
–
2, 5, 7,
38, 44
AGND
GND
GND
GND
–
–
1, 3, 8, Analog ground (0V)
37, 42
9, 16, 17, Ground
19, 22,
27, 29,
30, 35
-5.2V
+5V
NC
-5.2V
+5V
–
–
–
–
10, 13, -5.2V
25, 34
18, 28
+5V
12
No Connection
4
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
