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DEVICE SPECIFICATION
SONET/SDH CLOCK RECOVERY AND SYNTHESIS UNIT
BiCMOS PECL CLOCK GENERATOR SYNTHESIS UNIT
SONET/SDH CLOCK RECOVERY AND
GENERAL DESCRIPTION
S3014
S3014
FEATURES
• Complies with ANSI, Bellcore, and CCITT
specifications for jitter tolerance
• On-chip high frequency PLL with internal loop
filter for clock generation or clock recovery
• Supports clock generation for STS-3/STM-1
(155.52 MHz)
• Supports clock recovery for STS-3/STM-1
(155.52 Mbit/s) or STS-12/STM-4
(622.08 Mbit/s) NRZ data
• Selectable 19.44 MHz, 51.84 MHz, or
155.52 MHz reference frequency
• Lock detect—monitors transition density
and run length
• Low power
• Low-jitter ECL interface
• Small 44 PLCC or CLCC package
• TTL reference clock output
The function of the S3014 clock synthesis and recov-
ery unit is to derive high speed timing signals for
SONET/SDH-based equipment. The S3014 is imple-
mented using AMCC’s proven Phase Locked Loop
(PLL) technology.
In Clock Recovery mode, the S3014 receives either
an STS-3/STM-1 or STS-12/STM-4 scrambled NRZ
signal and recovers the clock from the data. The chip
outputs a differential ECL bit clock and retimed data.
In Clock Synthesis mode, the S3014 receives a
19.44, 51.84, or 155.52 MHz reference clock and out-
puts an STS-3/STM-1 or STS-12/STM-4 differential
ECL clock.
The S3014 utilizes an on-chip PLL which consists of
a phase detector, a loop filter, and a voltage con-
trolled oscillator (VCO). The phase detector
compares the phase relationship between the VCO
output and the REFCLK input, a loop filter converts
the phase detector output into a smooth DC voltage,
and the DC voltage is input to the VCO whose fre-
quency is varied by this voltage. A block diagram is
shown in Figure 1.
Figure 1. System Block Diagram
CAP1
CAP2
LOOP
FILTER
VCO
REFCKINP/N
TSTCLKEN
SEL(2:0)
2
2
3
CLOCK
DIVIDER
REFCKOUT
SERCLKOP/N
LOCK
DETECTOR
RST
LOCKDET
PHASE DETECTOR
2
SERDATOP/N
LOS
SERDATIP/N
2
1
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
