S3014
SONET/SDH CLOCK RECOVERY AND SYNTHESIS UNIT
CHARACTERISTICS
S3014 OVERVIEW
Performance
Clock Recovery Mode
The S3014 PLL complies with the minimum jitter toler-
ance for clock recovery proposed for SONET/SDH
equipment defined by the T1X1.6/91-022 document,
when used with differential inputs and outputs as
shown in Figure 2.
In the Clock Recovery mode, the S3014 supports
clock recovery for the STS-3/STM-1 and STS-12/
STM-4 rates. In this mode, ECL differential serial data is
input to the chip at the rate specified by the three SEL
pins, and clock recovery is performed on the incoming
data stream. An external ECL differential reference
clock (19.44, 51.84, or 155.52 MHz) is required to
minimize the PLL lock time and provide a stable output
clock source in the absence of serial input data.
Retimed data and clock are output from the S3014.
Input Jitter Tolerance
Input jitter tolerance is defined as the peak to peak
amplitude of sinusoidal jitter applied on the input sig-
nal that causes an equivalent 1 dB optical/electrical
power penalty. SONET input jitter tolerance require-
ments are shown in Figure 2. The measurement
condition is the input jitter amplitude which causes an
equivalent of 1 dB power penalty.
Clock Synthesis Mode
In the Clock Synthesis mode, the S3014 synthesizes up
to the STS-3/STM-1 and STS-12/STM-4 clock rates
from either a 19.44 MHz, 51.84 MHz, or 155.52 MHz
input reference frequency. STS-3/STM-1 jitter generation
is compliant with the SONET/SDH requirement for
0.01 U.I. (rms) maximum, given 14.1 ps (rms) jitter on
REFCLK in the 12 KHz to 1 MHz frequency band.
Jitter Generation
Jitter generation is defined as the amount of jitter at
the OC-N/STS-N output of a SONET equipment.
Jitter generation shall not exceed 0.01 UI rms in OC-3
mode and 0.03 UI rms in OC-12 mode when measured
using a highpass filter with a 12 kHz cutoff frequency.
In this mode, a crystal oscillator is connected to the
ECL differential reference input and synthesized up to
the output frequency selected using the three SEL
pins. The Clock Synthesis mode is recognized by the
absence of data on the SERDATIP/N input pins. In
this mode, tie the SERDATIP pin to ground and tie the
SERDATIN pin to VTT (-2.0v) or to an ECL low level.
A programmable internal divider outputs a TTL clock
at the same frequency as the reference clock input via
the REFCKOUT output. The lock detect output will
remain consistently low in the Clock Synthesis mode.
Serial Data Output Set-up and Hold Time
The output set-up and hold times are represented by
the waveforms shown in Figure 3.
Reference Clock Input
The required characteristics of the reference clock
are outlined below. Unless otherwise noted, specifi-
cations refer to both Clock Recovery and Clock
Synthesis modes of operation. While a single-ended
ECL reference clock may be used, additional jitter
due to edge movement related to threshold variations
from DC offsets may be induced.
Figure 2. Input Jitter Tolerance Specification
Sinusoidal
Input Jitter
Amplitude
Figure 3. Clock Output to Data Transition Delay
15
(UI p-p)
SERCLKOP/N
SERDATOP/N
1.5
0.15
t
h
t
su
f0
f2
f3
ft
f1
Frequency
Output Frequency
OC/STS
Level
f0
(Hz)
f1
(Hz)
f2
f3
ft
155.52 MHz
2.5 ns
622.08 MHz
450 ps
(Hz) (kHz) (kHz)
SERDATOP/N Setup Time
SERDATOP/N Hold Time
3
10
10
30
30
300
300
6.5
25
75
2.5 ns
650 ps
12
250
2
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
