S3014
SONET/SDH CLOCK RECOVERY AND SYNTHESIS UNIT
Performance Specifications
Parameter
Min
Typ
Max
Units
Condition
Given REFCLK = SERCLK ÷ 4,
12 or SERCLK ÷ 32 per SEL
<2:0> settings
Nominal VCO
Center Frequency
622.08
MHz
Clock Synthesis Output
Jitter
In CSU mode, given :
OC-3/STS-3
.005
.015
.01
64
UI(rms)
ps (rms)
•
56ps rms jitter on REFCLK
in 12 KHz to 1 MHz band
1
OC-12/STS-12
.03
48
UI(rms) • 14.1 ps rms jitter on REFCLK
ps (rms) in 12 KHz to 1 MHz band
Clock Recovery Output
Jitter
.01
UI(rms) rms jitter, in lock
Reference Clock
Frequency Tolerance
Clock Synthesis
2,3
Required to meet SONET output
-20
-100
20
100
ppm
ppm
frequency specification
Clock Recovery
OC-3/STS-3
OC-12/STS-12
Capture Range
±200
ppm
%
With respect to fixed reference
frequency
Lock Range
Clock Output
Duty Cycle
+8,-12
Minimum transition density of
20%
45
30
55
%
3
Acquisition Lock Time
OC-3/STS-3
OC-12/STS-12
64
16
With device already powered up
and valid REFCLK.
µsec
Reference Clock
Input Duty Cycle
% of
period
70
Reference Clock Rise &
Fall Times
2.0
ns
ps
10% to 90% of amplitude
ECL Output Rise & Fall
Times
10% to 90%, 50Ω to -2V
equivalent load, 5 pf cap
850
1. These specs can be achieved with either a 51.84 MHz or a 155.52 MHz Reference Clock.
2. Noise on REFCLK should be less than 14.1 ps rms in a jitter frequency band from 12 KHz to 1 MHz.
3. Specifications based on design values. Not tested.
Table 1. Mode Select
SEL2 SEL1 SEL0
SERCLKO
REFCKOUT
REFCKIN
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
622.08 MHz
622.08 MHz
622.08 MHz
622.08 MHz
155.52 MHz
155.52 MHz
51.84 MHz
19.44 MHz
19.44 MHz
—
51.84 MHz
19.44 MHz
51.84 MHz
19.44 MHz
19.44 MHz
155.52 MHz
51.84 MHz
19.44 MHz
6
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
