SONET/SDH OC-3/12 TRANSMITTER AND RECEIVER
S3005/S3006
Table 8. S3005 AC Timing Characteristics
(TA = -40°C to +85°C, VCC = 5 V ±5%, VEE = -4.5 V ±7% or -5.2V ± 5%)
Symbol
Description
Min
Max
Units
TSCLK Frequency (nom. 155, 311, or 622 MHz)
640
MHz
TSCLK Duty Cycle
40
33
60
67
%
%
PICLK Duty Cycle
tSPIN
tHPIN
tSLLD
tHLLD
PIN [7.0] Set-up Time w.r.t. PICLK
PIN [7.0] Hold Time w.r.t. PICLK
LLD Set-Up Time w.r.t. LLCLK
LLD Hold Time w.r.t. LLCLK
LLCLK Duty Cycle
2.0
1.0
100
100
40
ns
ns
ps
ps
%
60
tPTSD
tSTSD
tHTSD
tPPAE1
TSCLK Low to TSD Valid Propagation Delay
TSD Set-Up Time w.r.t. TSCLK
TSD Hold Time w.r.t. TSCLK
PCLK Low to PAE Valid Propagation Delay
TSD ± Edge Skew
440
ps
ps
ps
ns
ps
ps
400
400
3.0
100
100
TSD1
ESK
TSCLK1
TSCLK ± Edge Skew
ESK
1 Guaranteed but not tested.
Figure 10. PIN AC Input Timing
PICLK
Figure 11. LLD AC Input Timing
LLCLK
tS
tH
tS
tH
LLD
LLD
PIN
PIN
LLD
PIN[7:0]
1. When a set-up time is specified on TTL signals between an input and a clock, the set-up time is the time in picoseconds from the 50% point of the input to
the 50% point of the clock.
2. When a hold time is specified on TTL signals between an input and a clock, the hold time is the time in picoseconds from the 50% point of the clock to the
50% point of the input.
3. When a set-up time is specified on differential ECL signals between an input and a clock, the set-up time is the time in picoseconds from the cross-over
point of the input to the cross-over point of the clock.
4. When a hold time is specified on differential ECL signals between an input and a clock, the hold time is the time in picoseconds from the cross-over point
of the clock to the cross-over point of the input.
Figure 12. Output Timing
Figure 13. PAE Output Timing
PCLK
TSCLK
tP
tP
PAE
TSD
PAE
TSD+
Notes on TTL Output Timing
Notes on High-Speed PECL Output Timing
1. Output propagation delay time is the time in nanoseconds from the
50% point of the reference signal to the 30% or 70% point of the output.
2. Maximum output propagation delays are measured with a 15pF load on
the outputs.
1. Output propagation delay time is the time in nanoseconds from the cross-
over point of the reference signal to the cross-over point of the output.
Table 9. S3005 External Clock Mode Timing
Description
Min
Max
Units
REFCLK in Bypass Mode (nom. 155, 311, or 622 MHz)
640
MHz
REFCLK in Bypass Mode duty cycle
33
67
%
Applied Micro Circuits Corporation
22
6195 Lusk Blvd., San Diego, CA 92121 • (619) 450-9333
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
