SONET/SDH OC-3/12 TRANSMITTER AND RECEIVER
S3005/S3006
Table 10. S3006 AC Timing Characteristics
Symbol
Description
Min
Max
Units
1
POCLK Duty Cycle
40
60
%
POCLK Low to POUT [7:0] Valid Prop. Delay @ STS-3
POCLK Low to POUT [7:0] Valid Prop. Delay @ STS-12
0
0
5
1.5
ns
ns
tP
POUT
POCLK Low to FP Valid Propagation Delay @ STS-3
POCLK Low to FP Valid Propagation Delay @ STS-12
0
0
5
1.5
ns
ns
tP
FP
LLCLK Frequency
LLCLK Duty Cycle
640
60
MHz
%
40
LLCLK Low to LLD Valid Propagation Delay @ STS-3
LLCLK Low to LLD Valid Propagation Delay @ STS-12
-800
-500
800
500
ps
ps
tP
LLD
1 Driving CMOS with a 2.5V threshold and a 500Ω load, or driving TTL with a 1.4V threshold and a 150Ω load.
Figure 14. Input Timing - External Clock Mode
Figure 15. Output Timing Diagram
POCLK
RFCLK+
tP
POUT
tS
tS
tH
tH
RSD
DLD
RSD
DLD
POUT[7:0]
RSD
tP
FP
FP
DLD
LLCLK
Notes on Input Timing:
1. When a set-up time is specified between a data input and a
clock input, the set-up time is the time in picoseconds from the
crossover point of the differential data input to the crossover
point of the differential clock input.
tP
LLD
LLD
2. When a hold time is specified between a data input and a
clock input, the hold time is the time in picoseconds from the
crossover point of the differential clock input to the crossover
point of the differential data input.
Notes on Output Timing:
1. Output timing specification are valid when terminating all
outputs with 500Ω to GND.
2. Output propagation delay time of TTL outputs is the time in
picoseconds from the 50% point of the reference signal to
the 30% or 70% point of the output.
3. Maximum output propagation delays of TTL outputs are
measured with a 15 pF load on the outputs.
4. Output propagation delay time of high speed ECL outputs is
the time in picoseconds from the cross-over point of the
reference signal to the cross-over point of the output.
5. Maximum output propagation delays of TTL outputs are
measured with a 50Ω transmission line on the outputs.
Table 11. S3006 External Clock Mode Timing
Symbol
Description
REFCLK Freq. (Nominally 622/311//155 MHz)
REFCLK Duty Cycle
Min
Max
640
67
Units
MHz
%
33
tS
RSD to REFCLK Set-up Time
300
ps
RSD
REFCLK to RSD Hold Time @ STS-3
REFCLK to RSD Hold Time @ STS-12
1.0
100
ns
ps
tH
RSD
DLD to REFCLK Set-up Time
300
ps
tS
tH
DLD
REFCLK to DLD Hold Time @ STS-3
REFCLK to DLD Hold Time @ STS-12
1.0
100
ns
ps
DLD
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