S2068
DUAL GIGABIT ETHERNET TRANSCEIVER
Table 11. Power and Ground Signals Assignment and Descriptions
Pin Name
Qty.
Pin #
Description
Analog Power (VDD) low noise.
VDDA
3
B8 B13 C5
VSSA
VDD
3
3
8
A8 B4 C13
Analog Ground (VSS).
A10 B12 C6
Power for high speed circuitry (VDD).
Ground for high speed circuitry (VSS).
VSS
A3 A5 A7 A12
VSSSUB
A14 C8 C10 C12
PECLPWR
2
G14 J16
PECL Power (VDD).
PECL Ground (VSS).
PECLGND
DIGPWR
DIGGND
3
5
8
C16 D15 F16
B2 C1 D2 K16 N1 Core circuitry Power (VDD).
C3 D1 E2 E3 J14 Core circuitry Ground (VSS).
K15 P1 T1
TTLPWR
TTLGND
9
F1 G3 H1 M2 N3 Power for TTL I/O (VDD).
P9 R4 R8 T7
11
E1 F2 F3 K3 M3 Ground for TTL I/O (VSS).
N2 P3 T2 T4 T8
T11
PWR
GND
4
9
A2 A16 B1 B9
Power.
A6 A9 B3 B6 C9 Ground.
E16 F15 H15 H16
CAP1
CAP2
2
A15
B14
Pins for external loop filter capacitor.
NC
20
A1 B7 B16 C4 C7 Not connected. Used as Test Pins. Do Not Connect.
C15 D14 E14 F14
H14 P13 P14 R2
R9 R14 R15 T6
T9 T10 T16
12
October 13, 2000 / Revision D
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
