S2068
DUAL GIGABIT ETHERNET TRANSCEIVER
Figure 10. Transmitter Timing (REFCLK Mode, TMODE = 0)
REFCLK
DINx[0:9]
T1
T2
SERIAL DATA OUT
Table 12. S2068 Transmitter Timing (REFCLK Mode, TMODE = 0)
Parameters
Description
Min
0.5
1.3
Max Units
Conditions
T1
T2
Data Setup w.r.t. REFCLK
Data Hold w.r.t. REFCLK
ns
ns
See Note 1.
1. All AC measurements are made from the reference voltage level of the clock (1.4V) to the valid input or
output data levels (.8V or 2.0V).
Figure 11. Transmitter Timing (TBC Mode, TMODE = 1)
TBCx
DINx[0:9]
T1
T2
SERIAL DATA OUT
Table 13. S2068 Transmitter Timing (TBC Mode, TMODE = 1)
Parameters
Description
Min
1.0
0.5
Max Units
Conditions
9
0
O
0
S
1
I
C
D
E R
E
I
T1
T2
Data Setup w.r.t.
T
I
F
TBC
ns
ns
See Note 1.
Data Hold w.r.t. TBC
Phase drift between TBCx
and REFCLK
–3
+3
ns
1. All AC measurements are made from the reference voltage level of the clock (1.4V) to the valid input or
output data levels (.8V or 2.0V).
16
October 13, 2000 / Revision D
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
