DUAL GIGABIT ETHERNET TRANSCEIVER
S2068
Table 8. Receiver Input Signals Assignment and Descriptions
Pin Name
Level
I/O
Pin #
Description
RXAP
RXAN
Diff.
LVPECL
I
B5
A4
Differential LVPECL compatible inputs for channel A. RXAP is the
positive input, RXAN is the negative. Internally biased to VDD
-1.3V for AC coupled applications.
RXBP
RXBN
Diff.
LVPECL
I
B10
A11
Differential LVPECL compatible inputs for channel B. RXBP is the
positive input, RXBN is the negative. Internally biased to VDD
-1.3V for AC coupled applications.
Table 9. Receiver Control Signals Assignment and Descriptions
Pin Name
LPEN
Level
I/O
Pin #
Description
TTL
I
C14
Loopback Enable. When Low, input source for each channel is the
high speed serial output. When High, the serial output for each
channel is looped back to its input.
CMODE
TTL
I
C2
Clock Mode Control. When Low, the parallel output clocks
(RBC1/0x) rate equals 1/2 the data rate. When High, the parallel
output clocks (RBC1/0x) rate is equal to the data rate.
Note: All TTL inputs except REFCLK have internal pull-up networks.
Table 10. Mode Control Signal Assignment and Descriptions
Pin Name
Level
I/O
Pin #
Description
TESTMODE
TTL
I
D3
Test Mode Control. Keep Low for normal operation.
TESTMODE1
TMODE
TTL
TTL
I
I
L16
A13
Test Mode Control. Keep Low for normal operation.
Transmit Mode Control. When TMODE is Low, REFCLK is used
to clock data on DINx[0:9] into the S2068. When TMODE is
High, TBCx is used to clock data into the S2068.
CLKSEL
TTL
I
B11
REFCLK Select Input. This signal configures the PLL for the
appropriate REFCLK frequency. When CLKSEL=0, the REFCLK
frequency should equal the parallel word rate. When
CLKSEL=1, the REFCLK frequency should be 1/2 the parallel
data rate.
REFCLK
RESET
TTL
TTL
I
I
J15
Reference Clock is used for the transmit VCO and frequency
check for the clock recovered from the receiver serial data.
B15
When Low, the S2068 is held in reset. The receiver PLL is forced
to lock to the REFCLK. The FIFOs are initialized on the rising edge
of RESET. When High, the S2068 operates normally.
RATE
TTL
I
C11
When Low, the S2068 operates with the serial output rate equal
to the VCO frequency. When High, the S2068 operates with the
VCO internally divided by 2 for all functions.
Note: All TTL inputs except REFCLK have internal pull-up networks.
11
October 13, 2000 / Revision D
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
