DUAL GIGABIT ETHERNET TRANSCEIVER
S2068
Table 5. Transmitter Input Signals Assignment and Descriptions
Pin Name
Level
I/O
Pin #
Description
DINA9
TTL
I
T15
R13
P12
T14
R12
P11
T13
R11
T12
P10
Transmit Data for Channel A. Parallel data on this bus is clocked
in on the rising edge of TBCA or REFCLK.
DINA8
DINA7
DINA6
DINA5
DINA4
DINA3
DINA2
DINA1
DINA0
TBCA
TTL
TTL
I
I
R10
Transmit Byte Clock A. When TMODE is High, this signal is used
to clock Data on DINA[0:9] into the S2068. When TMODE is Low,
TBCA is ignored.
DINB9
DINB8
DINB7
DINB6
DINB5
DINB4
DINB3
DINB2
DINB1
DINB0
L15
L14
Transmit Data for Channel B. Parallel data on this bus is clocked in
on the rising edge of TBCB or REFCLK.
M16
M15
M14
N16
N15
N14
P16
P15
TBCB
TTL
I
R16
Transmit Byte Clock B. When TMODE is High, this signal is used
to clock Data on DINB[0:9] into the S2068. When TMODE is Low,
TBCB is ignored.
Note: All TTL inputs except REFCLK have internal pull-up networks.
Table 6. Transmitter Output Signals Assignment and Descriptions
Pin Name
Level
I/O
Pin #
Description
TXAP
TXAN
Diff.
LVPECL
O
D16
E15
High speed serial outputs for Channel A.
TXBP
TXBN
Diff.
LVPECL
O
O
G15
G16
High speed serial outputs for Channel B.
TCLKO
TTL
K14
TTL Output Clock at the parallel data rate. This clock is provided for
use by up-stream circuitry.
9
October 13, 2000 / Revision D
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
