S2060
GIGABIT ETHERNET TRANSCEIVER
Table 5. Pin Description and Assignment
Pin Name
Level
I/O
Pin #
Description
TX[9]
LVTTL
I
13
12
11
9
8
7
6
4
3
2
Transmit Data. Parallel data on this bus is clocked in on the
rising edge of TBC. TX[0] is transmitted first.
TX[8]
TX[7]
TX[6]
TX[5]
TX[4]
TX[3]
TX[2]
TX[1]
TX[0]
TBC
LVTTL
I
22
Transmit Byte Clock. Reference clock input to the PLL clock
multiplier. The frequency of TBC is the bit rate divided by 10.
When TESTEN is active, TBC replaces the VCO clock to
facilitate factory test. TBC should be supplied by a crystal
controlled reference since jitter on this line directly translates to
jitter on the output data.
RATEN
LVTTL
LVTTL
LVTTL
I
I
I
14
24
19
Rate Select. Active Low. This signal configures the PLL's for the
appropriate TBC frequency. When inactive, the device is in 1/2
rate mode. When active, the device is in full rate mode.
See Tables 2 and 4.
EN_CDET
EWRAP
Enable Comma Detect. Active High. When active, enables
detection of the COMMA sync pattern to set the word frame
boundary for the data to follow. When inactive, data is treated
as unframed.
Enable Wrap. When active, the transmitter serial data outputs
are internally routed to the receiver serial data inputs. TXP/N are
static (logic 1) in this state. When inactive, the RXP/N serial
inputs are selected (normal operation).
RXP
RXN
Diff.
LVPECL
I
I
54
52
(Externally Capacitively Coupled.) LVPECL Receive Serial Data
Inputs. RXP is the positive differential input, RXN is negative.
Internally biased to VCC -1.3 V.
-LCK_REF
LVTTL
27
Active Low. Lock to Reference Input. When inactive or open, the
receive PLL will lock to the incoming data (normal operation).
When active, the receive PLL is forced to lock to the TBC input.
March 7, 2001 / Revision H
6
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
