GIGABIT ETHERNET TRANSCEIVER
S2060
The COM_DET output signal is ACTIVE whenever
EN_CDET is active and the COMMA control charac-
ter is present on the RX[0:9] parallel data outputs.
The COM_DET output signal will be INACTIVE at all
other times.
Fibre Channel and Gigabit Ethernet Standards re-
quire that the COMMA sync character appears on
the rising edge of the RBC1 signal. In full rate mode
the phase of the data is adjusted such that this re-
quirement is met. No alignment is necessary when
the S2060 is operating in half rate mode since the
output clock frequency is equal to the parallel word
rate (RATEN INACTIVE).
Parallel Output Clock Rate and Data Stretching
The S2060 supports both full rate and half rate out-
puts, selected via the RATEN input. Table 4 shows
the operating rate scenarios. When RATEN is INAC-
TIVE, a data clock is provided on RBC1 at the data
rate. Data should be clocked on the rising edge of
RBC1. When RATEN is ACTIVE the device is in full
rate mode, and complementary TTL clocks are pro-
vided on the RBC0 and RBC1 outputs at 1/2 the
data rate as required by the Gigabit Ethernet Stan-
dard. Data is clocked on the rising edges of both
RBC0 and RBC1. See Figures 11 and 12.
In ethernet applications it is illegal for multiple con-
secutive COMMA characters to be generated. How-
ever, multiple consecutive COMMA characters can
occur in serial backplane applications. The S2060 is
able to operate properly when multiple consecutive
COMMA characters are received: after the first
COMMA is detected and aligned, the RBC0/RBC1
clock operates without glitches or loss of cycles.
Additionally, COM_DET stays high while multiple
COMMAS are being output.
Receive Latency
Table 4. Operating Rates
Parallel
Output Rate
(Mbps)
The average receive latency is 8 byte times.
Serial Input
Rate (Gbps)
RBC0
(MHz)
RCB1
(MHz)
RATEN
0
1
1.25
.625
62.5
N/A
62.5
62.5
125
62.5
March 7, 2001 / Revision H
5
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
