欢迎访问ic37.com |
会员登录 免费注册
发布采购

S2060B 参数 Datasheet PDF下载

S2060B图片预览
型号: S2060B
PDF下载: 下载PDF文件 查看货源
内容描述: 千兆以太网收发器 [GIGABIT ETHERNET TRANSCEIVER]
分类和应用: 网络接口电信集成电路电信电路以太网以太网:16GBASE-T
文件页数/大小: 22 页 / 696 K
品牌: AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
 浏览型号S2060B的Datasheet PDF文件第1页浏览型号S2060B的Datasheet PDF文件第3页浏览型号S2060B的Datasheet PDF文件第4页浏览型号S2060B的Datasheet PDF文件第5页浏览型号S2060B的Datasheet PDF文件第6页浏览型号S2060B的Datasheet PDF文件第7页浏览型号S2060B的Datasheet PDF文件第8页浏览型号S2060B的Datasheet PDF文件第9页  
S2060  
GIGABIT ETHERNET TRANSCEIVER  
mission characters1. For reference, Table 1 shows the  
mapping of the parallel data to the 8B/10B codes.  
S2060 OVERVIEW  
The S2060 transmitter and receiver provide serial-  
ization and deserialization functions for block en-  
coded data to implement a Gigabit Ethernet  
interface. The S2060 functional block diagram is de-  
picted in Figure 2. The sequence of operations is as  
follows:  
Loop Back  
Local loopback provides a capability for performing  
off-line testing. This is useful for ensuring the integ-  
rity of the serial channel before enabling the trans-  
mission medium. It also allows for system  
diagnostics.  
Transmitter  
1.10-bit parallel input  
2. Parallel-to-serial conversion  
3. Serial output  
1. A.X. Widmer and P.A. Franaszek, "A Byte Oriented DC Bal-  
anced (0,4) 8B/10B Transmission Code," IBM Research Report  
RC 9391, May 1982.  
Receiver  
1. Clock and data recovery from serial input  
2. Serial-to-parallel conversion  
3. Frame detection  
Table 1. Data Mapping to 8B/10B  
Alphabetic Representation  
4. 10-bit parallel output  
Data Byte  
The 10-bit parallel data input to the S2060 should be  
from a DC-balanced encoding scheme, such as the  
8B/10B transmission code, in which information to be  
transmitted is encoded 8 bits at a time into 10-bit trans-  
TX[0:9] or RX[0:9]  
0
a
1
b
2
c
3
d
4
e
5
i
6
f
7
g
8
h
9
j
8B/10B  
Alphabetic Representation  
Figure 2. Functional Block Diagram  
S2060  
FIFO  
(4 x 10)  
10  
10  
TX[0:9]  
Shift  
Register  
TXP  
TXN  
PLL Clock  
Multiplier w/  
lock detect  
F0 = F1 x 10  
TBC  
Shift  
D
RATEN  
Register  
PLL Clock  
2:1  
Recovery w/  
lock detect  
10  
Q
RXP  
RXN  
RX[0:9]  
D
EWRAP  
-LCK_REF  
COMMA  
Detect  
Logic  
Control  
Logic  
COM_DET  
RBC0  
EN_CDET  
RBC1  
March 7, 2001 / Revision H  
2
 复制成功!