GIGABIT ETHERNET TRANSCEIVER
S2060
Table 5. Pin Description and Assignment (Continued)
Pin Name
Level
I/O
Pin #
Description
RX[9]
LVTTL
O
34
35
36
38
39
40
41
43
44
45
Receive Data Outputs. For full rate output, parallel data on this bus
is valid on the rising edges of RBC0 and RBC1. RX[0] is the first
bit received.
RX[8]
RX[7]
RX[6]
RX[5]
RX[4]
RX[3]
RX[2]
RX[1]
RX[0]
RBC1
RBC0
LVTTL
LVTTL
O
O
30
31
Complementary Receive Byte Clocks. In full rate mode, parallel
receive data is valid on the rising edges of RBC0 and RBC1 (see
Figure 8, timing diagram). For half rate, output data is valid on the
rising edge of RBC1. See Table 4.
COM_DET
47
Comma Detect. Active High. When EN_CDET is active,
COM_DET indicates that the sync character is present on the
parallel bus bits RX[0:9]. Upon detection of the COMMA sync
character (0011111xxx positive polarity) this output data is valid
on the rising edge of RBC1 and remains active for one RBC1 clock
period. When EN_CDET is inactive, COM_DET is held inactive
(logic 0). Upon change of state of the EN_CDET input, the
COM_DET output response will be delayed by a maximum of 3
byte times.
TXP
TXN
Diff.
LVPECL
O
62
61
Transmit Serial Data. These lines are static (TXN HIGH, TXP
HIGH) when EWRAP is active. These lines are static (TXN HIGH,
TXP LOW) when TXRST is active. Upon startup, these outputs are
held static (TXN HIGH, TXP LOW) until the TXPLL has locked to
the reference clock. Each output can drive 150 Ω to ground.
S2060A, S2060B, S2060D Specific Pins
DNC
16, 17, Not connected. Note that pin 48 cannot be tied high. It must be
48, 49
open or held low.
S2060C Specific Pins
TC1
TC0
16
17
Transmit Capacitor. External capacitor connections for transmitter
internal PLL filter. The recommended valueof this external
capacitor is 2 nF (a value of 1 nF can also be used). If desired, the
external capacitor may be omitted with no loss in performance.
RC0
RC1
48
49
Receiver Capacitor. External capacitor connections for receiver
internal PLL filter. The recommended value of this external
capacitor is 2 nF (a value of 1 nF can also be used). If desired, the
external capacitor may be omitted with no loss in performance.
Note that pin 48 cannot be tied high. It must be open (as
recommended with external capacitor) or held low.
Note: All TTL inputs have internal 15 KΩ pull-up networks.
March 7, 2001 / Revision H
7
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
