S2046/S2050
GIGABIT ETHERNET CHIPSET
Figure 11. Transmitter Timing Diagram (10-bit Mode)
REFCLK
D[10:19] 10 BIT DATA
T
T
2
1
D19
D9
1
3
5
7
11
13
15
17
SERIAL
DATA OUT
2
4
6
8
12
14
16
18
D0
D10
Figure 12. Receiver Timing Diagram (20-bit Mode)
REFCLK
T
T
4
3
D[0:19]
D19
1
3
5
7
9
11
13
15
17
SERIAL
DATA OUT
2
4
6
8
10
12
14
16
18
D0
Figure 13. Receiver Timing Diagram (10-bit Mode)
D9
D19
18
1
3
5
7
11
13
15
17
SERIAL DATA IN
2
4
6
8
12
14
16
D10
D0
REFCLK (125 MHz)
RCLK (62.5 MHz)
RCLKN (62.5 MHz)
T
5
D[10:19] and SYNC
K28.5
DATA
T
T
7
T
6
T
6
7
Figure 14. Receiver Timing Diagram (20-bit Mode)
D19
18
1
3
5
7
9
11
10 12
13
15
17
SERIAL
DATA IN
2
4
6
8
14
16
D0
REFCLK
RCLKN
D[0:19] and SYNC
T
T
8
9
March 29, 2000 / Revision B
17
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
