S2046/S2050
GIGABIT ETHERNET CHIPSET
Table 13. Receiver Timing
Parameters
Description
Min
Max Units
Conditions
8B/10B IDLE pattern, sample
basis.
TLock Startup
SDR, RSDF
Data Acquision Lock Time at Startup
Serial Input Data Rise and Fall Time
-
2.5
µs
20% to 80% tested on a
sample basis.
R
-
300
ps
ns
T5
RCLKN to RCLK Skew
1.5
2.5
1.5
2.1
6.3
-
-
-
T6
Data Setup w.r.t. RCLK/RCLKN
Data Hold w.r.t. RCLK/RCLKN
Data Setup w.r.t. RCLKN
Data Hold w.r.t. RCLKN
Data Output Rise Time
ns 10 Bit (see note).
ns 10 Bit (see note).
ns 20 Bit (see note).
ns 20 Bit (see note).
ns 0.8 to 2.0V, 10 pF load.
ns 0.8 to 2.0V, 10 pF load.
ns
T7
-
T8
-
T9
-
TDR
2.4
2.4
3.0
3.0
60
TDF
Data Output Fall Time
-
TR
RCLK/RCLKN Rise Time
RCLK/RCLKN Fall Time
RCLK/RCLKN Duty Cycle
-
TF
-
ns
Duty Cycle
40
%
Jitter Tolerance. Input data eye
opening allocation at receiver for
BER 1E-12.
As specified in IEEE 802.3z
(see Figure 19).
TJ
599
370
ps
Determinstic Jitter Tolerance.
Deterministic component of input jitter
for jitter tolerance measurement
As specified in IEEE 802.3z
(see Figure 19).
TDJ
ps
Note: All AC measurements are made from the reference voltage level of the clock (1.4V) to the valid input or output data
levels (.8V or 2.0V).
March 29, 2000 / Revision B
16
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
