S2046/S2050
GIGABIT ETHERNET CHIPSET
Table 12. Reference Clock Requirements
Parameters
Description
Frequency Tolerance S2046
Frequency Tolerance S2050
Symmetry
Min
Max Units
Conditions
FT
FT
-100 +100
-100 +100
ppm
ppm
%
–
–
TD1-2
40
0.5
-
60
3.2
100
Duty Cycle at 50% pt.
20-80%
T
RCR, TRCF
–
REFCLK Rise and Fall Time
Random Jitter
ns
ps
Peak-to-Peak
Table 13. Transmitter Timing
Parameters
Description
Min
Max Units Conditions
T1
T2
T3
T4
Data Setup w.r.t. REFCLK
Data Hold w.r.t. REFCLK
Data Setup w.r.t. REFCLK
Data Hold w.r.t. REFCLK
2.0
1.0
2.0
2.0
-
-
-
-
ns
ns
ns
ns
10 Bit.1
10 Bit.1
20 Bit.1
20 Bit.1
Peak-to-peak tested on a sample
basis, 27–1 pattern.
Total Jitter
Serial Data Output Total Jitter
-
192
ps
Peak-to-peak tested on a sample
basis, IDLE pattern. Note: Random
jitter is not measured, but can be
calculated to be 112 ps p-p.
Serial Data Output
Determinsitic Jitter
TDJ
-
80
ps
Serial Data Rise and Fall
Time
20% to 80% tested on a sample
basis.
T
SDR, TSDF
-
-
300
20
ps
ns
Rise, fall of SYNCEN input must not
exceed this value.
TSYNCEN
SYNCEN Rise and Fall Time
1. All AC measurements are made from the reference voltage level of the clock (1.4V) to the valid input or output data levels
(.8V or 2.0V).
March 29, 2000 / Revision B
15
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
