S2042/S2048
HIGH PERFORMANCE SERIAL INTERFACE CIRCUITS
Figure 15. Receiver Timing Diagram (1062.5 Mbps 10-bit mode)
D19
18
D19
18
11
13
15
17
11
13
15
17
SERIAL
DATA IN
12
14
16
12
14
16
D10
D10
REFCLK
RCLKN
1.4V
RCLK
T
3
2.0V
.8V
D[0:19]
K28.5
DATA
SYNC
T
T
5
T4
4
T
5
Figure 16. Receiver Timing Diagram (1062.5 Mbps, 20-bit mode)
D19
1
3
5
7
9
11
10 12
13
15
17
SERIAL
DATA IN
2
4
6
8
14
16
18
D0
REFCLK
RCLK
RCLKN
T
3
D[0:19]
and SYNC
T
T
6
7
April 10, 2000 / Revision B
21