S2042/S2048
HIGH PERFORMANCE SERIAL INTERFACE CIRCUITS
Table 13. S2042 Transmitter Timing
Parameters
T1
Description
Data Setup w.r.t. REFCLK
Data Hold w.r.t. REFCLK
Data Setup w.r.t. REFCLK
Data Hold w.r.t. REFCLK
Data Setup w.r.t. REFCLK
Min
1.0
1.0
2.0
5
Max Units
Conditions
4.0
ns
ns
ns
ns
ns
T2
T3
T4
T5
-
-
-
-
1
10% to 90% tested on a
sample basis
TCR, TCF
TCLK Rise and Fall Time
Serial Data Rise and Fall
-
-
5.0
ns
ps
20% to 80% tested on a
sample basis
TSDR, TSDF
320
T6
Data Hold w.r.t. REFCLK
TCLK, TCLKN Duty Cycle
-
1.5
60
ns
%
Tested on a sample basis.
–
TDC
40
Transmitter Output Jitter Allocation
RMS, tested on a sample
basis. Measured with 1010
pattern.
Serial Data Output Random Jitter
(RMS)
TJRMS
TDJ
-
-
20
ps
ps
Peak-to-peak, tested on a
sample basis. Measured with
IDLE pattern.
Serial Data Output Deterministic Jitter
(p-p)
100
Note: All AC measurements are made from the reference voltage level of the clock (1.4 V) to the valid input or output data levels (.8 V
or 2.0 V). All TTL AC measurements are assumed to have the output load of 10 pF.
April 10, 2000 / Revision B
16
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
