S2042/S2048
HIGH PERFORMANCE SERIAL INTERFACE CIRCUITS
Table 14. S2048 Receiver Timing
Parameters
T3
Description
RCLK to RCLKN skew
Data Setup Time
Min
-
Max Units
Conditions
1
-
ns
ns
ns
Tested on a sample basis.
10 Bit Mode, 1062 Mbps
10 Bit Mode, 1062 Mbps
T4
T5
3.0
1.5
Data Hold Time
-
20 Bit Mode, 531, 266 Mbps
20 Bit Mode, 531, 1062 Mbps
T6
T7
Data Setup Time
2.5
7.5
-
-
-
ns
ns
ns
20 Bit Mode, 531, 266 Mbps
20 Bit Mode, 531, 1062 Mbps
Data Hold Time
10% to 90% tested on a
sample basis
T
RCR, TRCF
RCLK Rise and Fall Time
5.0
10% to 90% tested on a
sample basis
TDR, TDF
Data Output Rise and Fall Time
Serial Data Input Rise and Fall
-
5.0
300
2.5
ns
ps
µs
T
SDR, TSDF
-
-
20 to 80%.
Data acquisition lock time at
<1.0625 Gbps
8B/10B IDLE pattern sample
basis.
TLOCK
Duty Cycle
RCLK/RCLKN Duty Cycle
40%
60%
As specified in Fibre Channel
FC-PH standard eye diagram
jitter mask.
Input Jitter
Tolerance
Input data eye opening allocation at
receiver input for BER </– 1E–12
Bit
Time
30%
-
Note: All AC measurements are made from the reference voltage level of the clock (1.4 V) to the valid input or output data levels
(.8 V or 2.0 V) and have the output load of 10 pF.
April 10, 2000 / Revision B
17
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
