S2042/S2048
HIGH PERFORMANCE SERIAL INTERFACE CIRCUITS
Figure 11. Transmitter Timing Diagram (1062.5 Mbps, 10-bit mode)
REFCLK (106.25 MHz)
D[10:19]
T
T
T
T
2
3
4
5
TCLKN (53.125 MHz)
TCLK (53.125 MHz)
T
6
T
1
D19
D19
11
13
15
17
11
13
15
17
SERIAL
DATA OUT
12
14
16
18
12
14
16
18
D10
D10
Figure 12. Transmitter Timing Diagram (1062.5 Mbps, 20-bit mode)
REFCLK (53.125 MHz)
D[0:19]
T
T
3
2
T
T
4
5
TCLKN (53.125 MHz)
T
T
6
1
TCLK (53.125 MHz)
D19
1
3
5
7
9
11
13
15
17
SERIAL
DATA OUT
2
4
6
8
10
12
14
16
18
D0
April 10, 2000 / Revision B
19