欢迎访问ic37.com |
会员登录 免费注册
发布采购

S2047B-5 参数 Datasheet PDF下载

S2047B-5图片预览
型号: S2047B-5
PDF下载: 下载PDF文件 查看货源
内容描述: [Interface Circuit, PQFP52, 10 X 10 MM, COMPACT, PLASTIC, QFP-52]
分类和应用: 电信电信集成电路
文件页数/大小: 23 页 / 165 K
品牌: AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
 浏览型号S2047B-5的Datasheet PDF文件第14页浏览型号S2047B-5的Datasheet PDF文件第15页浏览型号S2047B-5的Datasheet PDF文件第16页浏览型号S2047B-5的Datasheet PDF文件第17页浏览型号S2047B-5的Datasheet PDF文件第19页浏览型号S2047B-5的Datasheet PDF文件第20页浏览型号S2047B-5的Datasheet PDF文件第21页浏览型号S2047B-5的Datasheet PDF文件第22页  
S2046/S2047  
GIGABIT ETHERNET CHIPSET  
Timing  
When a 62.5 MHz module is in frequency lock (either  
with REFCLK or a serial data stream) RCLKN shall  
never have a high level duration (>2.0 v) which is  
less than 6.0 ns, nor a low level duration (<0.8 v)  
which is less than 5.5 ns (no clock shivering shall  
occur). At byte realignment, RCLKN clock states are  
to be extended rather than truncated). When the  
S2047 is in frequency lock (either with REFCLK or a  
serial data stream) and LOCK_REF has been inac-  
tive for at least 2500 baud times the minimum  
instantaneous period shall always be greater that 16.0  
ns. When the PLL is adjusting to a new phase or a  
new frequency, where both the old and new frequen-  
cies are valid Gigabit Ethernet frequencies, RCLKN  
shall never have a period less than 16.0 ns.  
This section will detail the timing requirements of all  
of the signals on the interface. All timing is measured  
into a lumped 35 pf capacitive load.  
RBC[N] Timing  
When LOCK_REF is pulled low, RCLKN should be in  
local phase lock with TBC within 500 µs. LOCK_REF,  
when activated, shall stay low for a duration of at  
least 500 µs if receiver frequency lock is to be ex-  
pected. After local phase lock has been acquired,  
and when EWRAP is high, 2500 baud times after  
LOCK_REF is driven high, RCLKN shall be in phase  
lock with REFCLK. After local phase lock has been  
acquired, and when EWRAP is low, 250 baud times  
after LOCK_REF is driven high, RCLKN shall be in  
phase lock with the incoming serial data stream.  
Figure 10. RCLKN Timing Diagram  
Table 13. Serial Data Input Timing Table (RLX, RLY; RX, RY)  
Parameters  
Description  
Min  
Max  
Units  
Conditions  
R
, R  
SDF  
Serial data input rise and fall  
300  
2.4  
ps  
20% to 80%.  
SDR  
T
Data acquisition lock time @  
<1.0625Gb/s  
µs  
LOCK  
8B/10B IDLE pattern sample basis  
bit time  
Input Jitter  
Tolerance  
Input data eye opening  
allocation at receiver input  
for BER 1E–12  
As specified in Fibre Channel FC–PH  
standard eye diagram jitter mask.  
(See Figure 12.)  
30%  
For BER IE-9 see Figure 14.  
May 16, 2000 / Revision NC  
18  
 复制成功!