S2046/S2047
GIGABIT ETHERNET CHIPSET
Table 11. REFCLK Timing Table
Parameter
Symbol
Min
Max
Units
Conditions1
Frequency
62.49375
124.9875
62.50625
125.0125
This is dependent on
the data path width.
62.50 MHz
f
MHz
125.00 MHz
Jitter
1250.0 MBaud
ps
pk-pk
160
Period (f=62.5 MHz)
Period (f=125.0 MHz)
REFCLK Low Time
REFCLK High Time
TX Setup to REFCLK
tp
tp
15.9984
7.9992
3.2
16.0016
8.0008
ns
ns
ns
ns
ns
tlow
thigh
ts
3.2
2
TX Hold From
REFCLK
th
tr
tf
2
ns
ns
ns
This applies to the
REFCLK input.
REFCLK Rise Time
REFCLK Fall Time
0.5
0.5
3.2
3.2
This applies to the
REFCLK input.
1. All parameters are for outputs driven into a 35pF lumped capacitive load.
Table 12. Serial Data Timing Table (TLX, TLY, TX, TY)
Parameters
Description
Min
Max Units
Conditions
Serial data output random
jitter (RMS)
TJRMS
RMS, tested on a sample basis.
Measured with 1010 pattern.
20
ps
Serial data output
Peak-to-peak, tested on a sample
basis.
TDJ
deterministic jitter (p-p)
100
300
ps
ps
Measured with IDLE pattern.
T
SDR,TSDF
Serial data rise and fall
20% to 80%, tested on a sample
basis.
Tested per Figure 10.
May 16, 2000 / Revision NC
17
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
