S2046/S2047
GIGABIT ETHERNET CHIPSET
ments of REFCLK with respect to the TX[10:19]
(TX[0:9]) signals, minimum high and low durations,
and the rising and falling slew rate magnitudes. In
addition, this system supplied clock must not have
more jitter than ±20% of a baud interval.
Timing
The data on the TX[00:09] (TX[00:19]) data bus will
be sampled on every rising edge of REFCLK. The
data will be serialized and transmitted onto the serial
link. The figure below illustrates the timing require-
Figure 9. REFCLK Timing Diagram
May 16, 2000 / Revision NC
16