HIPPI
S2020/S2021 SOURCE DEVICE STATE MACHINES
to the standard transitions, this state is exited to the
{HSEQER} state if the “DXFR” decode is true, to
the {ILLINPT} state if the “HIFL” decode is true, to
the {ENDBPKT} state if the
{ILLINPT} The ILLegal INPuT signals state is entered
from all other states except the {HSEQER} state if
the “CERR” decode is true. For specific states other
decodes incorrect that state will also force the
{ILLINPT} state. In this state the Sequence Error
status word is presented to the data outputs of the
Desination device. During this state the
<RSTCON> signal is generated to force the reset
of the Connect Control SM and abandon the com-
promised HIPPI Connection. This state is exited to
the {DISCON0} state unconditionally on the next
clock cycle.
“IDLG” decode is true, or to the {ENDBST} state if
the “GLRC” decode is true.
{ENDBST} The END BurST state is entered from the
{LLRCCH} state if the “GLRC” decode is true. In
this state the general op status word is presented
on the data outputs of the Destination device. In
addition to the standard transitions, this state is ex-
ited to the {ILLINPT} state if the “HIFL” decode is
true, to the {DTATRNSF} state if the “DXFR” de-
code is true, to the {IBSTGP} state if the “GLRC”
decode is true, or to the {INTRPKT} state if the
“IDLG” state is true.
4.3 HOST DATA/FIFO SM EXTERNAL OUT-
PUTS
PKOUT PacKet OUT signal to the Destination Host
system. A ‘1’ on this signal indicates the detection
and sychronization of an asserted PKT signal from
the HIPPI channel. A ‘0’ indicates the end of a
HIPPI Packet.
{IBSTGP} The Inter BurST GaP state is entered from
the {ENDBST} state if the “GLRC” decode is true.
This state persists if the “GLRC” decode remains
true. In this state the general op status word is
presented on the data outputs of the Destination
device. In addition to the standard transitions, this
state is exited to the {ILLINPT} state if the “HIFL”
decode is true, to the {DTATRNSF} state if the
“DXFR” decode is true, or to the {INTRPKT} state if
the “IDLG” decode is true.
BROUT BuRst OUT stignal to the Destination Host
system. A ‘1’ on this signal indicates the detection
and synchronization of an asserted BRST signal
from the HIPPI channel. A ‘0’ indicats a deasserted
BRST signal.
DTVAL DaTa VALid signal to the Destination Host
system. This signal is at a ‘1’ when new data or
status is available on the data outputs of the Desti-
nation device. This signal is at ‘0’ in the {IDLE},
{IBSTGP}, and {PKTNBST} states.
{INTRPKT} The INTeR PacKeT state isentered from
the {IBSTGP} state or from the {ENDBST} state if
the “IDLG” decode is true. In this state the general
op status word is presented on the data outputs of
the Destination device. In addition to the standard
transistions, this state is exited to the {HSEQER}
state if the “DXFR” decode is true, to the {ILLINPT}
state if the “HIFL” decode is true, to the {BGNPKT}
state if the “GLRC” decode is true, or to the {IDLE}
state if the “IDLG” decode is true.
SELB0-2 SELect Bus 0, 1, 2 signals’ to the Destination
Host system. These signals are intended to be the
primary addressing delimiters of the various status
and data words presented at the data outputs of
the Destination device. The functions of these sig-
nals are described in the S2020/S2021 Preliminary
Device Specification.
{HSEQER} The HIPPI SEQuence ERror state is en-
tered unconditionally if the OVERFLOW condition
occurs (Burst received when Burst and Ready
counters are equal). The {HSEQER} is also entered
from all states except {ILLINPUT}. For specific
states other decodes incorrect that state will also
froce the {HSEQER} state. In this state the Se-
quence Error status word is presented to the data
outputs of the Desination device. During this state
the <RSTCON> signal is generated to force the
reset of the Connect Control SM and abandon the
compromised HIPPI Connection. This state is ex-
ited to the {DISCON0} state unconditionally on the
next clock cycle.
www.amcc.com
27
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
