HIPPI
S2020/S2021 SOURCE DEVICE STATE MACHINES
Figure A-1. Source Flow Diagram
S1100
Power-up or system
master reset
S1110
Check for
MODE 0 THEN MODE 2
CON SM: {NODEST}
H D/F SM: {INIT}
INTERCONNECT = true
MODE 3
CON SM: {INIT}
H D/F SM: {INIT}
S1120
Inform SMT that
INTERCONNECT = true
S1130
Idle, wait for a ULP
connection request
MODE 2
CON SM: {INIT}
H D/F SM: {INIT}
CON SM: {IDLE}
H D/F SM: {INIT}
S1140
Wait for
INTERCONNECT = true
S1150
Source ULP requests a
connection
MODE 0 THEN MODE 2
CON SM: {NODEST}
H D/F SM: {INIT}
CON SM: {REQ}
H D/F SM: {RD IFL},
{PST IFL}
S1160
Inform SMT that
INTERCONNECT went
false
S1170
S1180
Connection in process,
wait for destination
CON SM: {LOST DEST}
H D/F SM: {DESTERR}
Connection request
aborted by source
CON SM: {REQ}
H D/F SM: {PST IFL}
CON SM: {ABORT}
H D/F SM: {INIT}
S1190
Destination responded with
CONNECT = true
S1200
Destination rejected the
connection request
CON SM: {CON 1-16}
H D/F SM: {PST IFL}
CON SM: {REJECT}
H D/F SM: {PST IFL}
S1210
Destination accepted the
connection request
CON SM: {CONNECTED}
H D/F SM: {IDLE}
From
S1230
From
S1260
To
S1280
To
S1220
www.amcc.com
28
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
