S2009
1.6 GBPS QUAD SERIAL BACKPLANE DEVICE
Table 20. S2009 Receiver Timing (Full and Half Clock Mode)
Parameter
Description
Min
Max Units
Conditions
2.5
1.5
ns
ns
1.3 Gbps
1.5552 Gbps
T3
T4
T5
T6
T7
Data Setup w.r.t. RCxP/N
Data Hold w.r.t. RCxP/N
Data Setup w.r.t. RCxP/N
Data Hold w.r.t. RCxP/N
1.5
ns
ns
ns
2.5
1.0
at 1.3 Gbps
at 1.5552 Gbps1,2
1.0
Time from RCxP rise to
RCxN rise
7.5
5.8
8.5
7.8
ns
ns
at 1.3 Gbps
at 1.5552 Gbps1,2
TRP, TFP
TRN, TFN
RCxP Rise and Fall Times
RCxN Rise and Fall Times
DOUTx Rise and Fall Times
RCxP/N Duty Cycle
900
900
2.4
60
ps
ps
ns
%
See note 2. See Figure 19.
See note 2. See Figure 19.
See note 2. See Figure 19.
See note 1.
TDR, TDF
Duty Cycle
40
1. Measurements made from the reference voltage levels of the clock (1.4 V) to the valid input or output data levels (0.8 V or 2.0 V).
2. TTL/CMOS AC timing measurements are assumed to have an output load of 10 pF.
34
February 9, 2001 / Revision C
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
