1.6 GBPS QUAD SERIAL BACKPLANE DEVICE
S2009
When operating in independent mode, PLL “Loss of
Lock” status for each channel is indicated by a continu-
ous 1-0-1 on its respective ERR, EOF, and KFLAG
outputs. LOLx will report a logic 1 asynchronously
when “Loss of Lock” occurs. When operating in the
Channel Lock Mode, PLL locking of all four channels
must be accomplished before byte-skewing is achieved
and “Channel Lock Detected” status can be indicated
on the ERR, EOF, KFLAG, and LOL outputs.
Channel Lock Mode Synchronization
Incidental errors occurring in the received data can
transform a normal data character into a K28.5 char-
acter. To prevent this occurrence from making the
channel locking process unnecessarily vulnerable to
bit errors, the S2009 implements a channel lock
state machine for each channel with linkage between
channels to move to the final deskewed state.
The Channel Lock state diagram is shown in Figure
7. The S2009 powers up in the “No Sync” state.
When in the “No Sync” state, each channel of the
S2009 is actively searching the received data stream
for the occurrence of a K28.5 and will align its de-
multiplexer to the character when detected, and will enter
the “Acquiring Sync” state. K28.5 will be reported on each
channel as 0-1-1 (err-eof-kflag). When four or more con-
secutive K28.5 characters are received on a given chan-
nel, the channel will enter the “Re-sync” state as shown in
Figure 7. “Re-sync” state status will be reported as 1-1-1
until the S2009 deskewing circuitry has aligned the
data output from each channel such that the first valid
non-errored codeword (or data character) other than
a K28.5 for each channel is output simultaneously1. The
device will move to the “In Sync” state and indicate chan-
nel lock status by each channel as a 0-1-0. See Figure 8.
Note that “Re-sync” is reported independently by each
channel regardless of the state of the other channels.
However, “In Sync” can only be reported when all four
channels are in the “In Sync” state and detect a valid data
character within the deskew window2. The “In Sync” state
is reported simultaneously for each channel as 0-1-0.
Reference Clock Input
A single reference clock, which serves both transmit-
ter and receiver, must be provided from a low jitter
clock source. The frequency of the received data
stream (divided-by-20) must be within ±100 ppm of
the reference clock to insure reliable locking of the
receiver PLL.
Serial-to-Parallel Conversion
Once bit synchronization has been attained by the
S2009 CRU, the S2009 must synchronize to the 10-
bit word boundary. Word synchronization in the
S2009 is accomplished by detecting and aligning to
the 8B/10B K28.5 codeword. The S2009 will detect
and byte-align to either polarity of the K28.5. Each
channel of the S2009 will detect and align to a K28.5
anywhere in the data stream. Two modes of opera-
tion are supported: Normal Mode, in which the chan-
nels operate independently and Channel Lock Mode,
in which the channels are locked together to form a
virtual 32-bit interface.
For Channel Lock operation, the S2009 must provide
an additional level of synchronization to insure that
differences in delay encountered by the four channels
do not result in parallel output data from each channel
leading or lagging by one parallel clock cycle. In
Channel Lock Mode, assertion of DNA results in the
K28.5 being transmitted simultaneously on all four
channels. Each receiver provides a FIFO buffer and
adjusts the delay through this buffer to ensure that the
first data following the K28.5 is output simultaneously
from the receiver on the parallel interface. Table 7
details the function of the EOF, KFLAG, ERR, and
LOL pins in status reporting. For Channel Lock opera-
tion, a single output clock, RCA P/N, is provided syn-
chronous with the data. The other RCx P/N clocks will
be frequency locked, but will have an arbitrary phase
relationship with the data.
Once the S2009 has entered the “In Sync” state, it will
report status but will not alter the relative skew of the
output FIFOs. The S2009 will exit the “In Sync” state and
move to the “No Sync” state if one of the four CRUs
reports a loss of lock, if the 8B/10B decoder observes five
consecutive decoding errors, or if the decoder error rate
>50% in a block of 16 codewords. The error rate of
greater than 50% in a block of 16 and five or more se-
quential decoding errors is calculated on a per K28.5
basis. The error counter resets whenever a K28.5 char-
acter is received or an unlock condition occurs. The
device can also be put in the “No Sync” state by setting
TCLKD=Low for at least 16 clocks, or by asserting
RESET_N Low.
1. Note, if the S2009 does not have to delay any of the channels
for word alignment, “Re-sync” reporting (1-1-1) will not be seen
and Channel Lock status will be reported simultaneously on the
four channels as 0-1-0.
2. Note when CMODE = 0, if the deskew window to channel lock
is exceeded, indeterminate status will be reported.
11
February 9, 2001 / Revision C
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
