Revision J – April 7, 2006
S2004 – Quad Serial Backplane Device
Data Sheet
Data Output
CHANNEL LOCKING/RE-LOCKING
PROCEDURE
Data is output on the DOUT[0:7] outputs. K-characters
are flagged using the KFLAG signal. The EOF (with
KFLAG) is used to indicate the reception of a valid
K28.5 character. Invalid codewords and decoding
errors are indicated on the ERR output. KFLAG, EOF,
and ERR are buffered with the data in the FIFO to
insure that all outputs are synchronized at the S2004
outputs. Errors are reported independently for each
channel in both CHANNEL-LOCK mode and NOR-
MAL mode operation.
The Channel locking/relocking procedures are sum-
marized below. Following these procedures will in-sure
proper CHANNEL LOCK operation of the device.
When powered up, the S2004 will lock to the received
data within approximately 2500 bit times. The CRU
must report lock for approximately 32,000 REFCLK
periods (320 µs) before channel locking is enabled.
1. Insure that the S2004 is in the “No Sync” state.
This can be accomplished by resetting the device
by toggling TCLKD low, or by de-asserting the
channel lock for several clock periods and then re-
asserting.
The S2004 TTL outputs are optimized to drive 65 line
impedances. Internal source matching provides good
performance on unterminated lines of reason-able
length.
2. Transmit
the
appropriate
synchronization
Parallel Output Clock Rate
sequence. Four K28.5 characters or the 16 word
SYNC sequence can be used to de-skew the
DOUT FIFOs. The 16 word SYNC character can
be generated by asserting SYNC=1 and DN=1.
Two output clock modes are supported, as shown in
Table 8. When CMODE is High, a complementary TTL
clock at the data rate is provided on the RCxP/N out-
puts. Data should be clocked on the rising edge of
RCxP. When CMODE is Low, a complementary TTL
clock at 1/2 the data rate is provided. Data should be
latched on the rising edge of RCxP and the rising edge
of RCxN.
3. Wait for “channel lock detected” as defined by
Table 7.
The S2004 will enter the “No Sync” state if: any CRU
loses lock, if the CH_LOCK signal is de-asserted, if
four or more consecutive decoder errors are observed,
or if the decoder error rate exceeds 50% in a block of
16 bytes, or if TCLKD is low. If desired, the CRU lock
status of each channel can be checked by de-assert-
ing CH_LOCK and confirming that “Loss of Sync”
status (Table 7) is not reported by any channel. To
reacquire Sync after moving to the “No Sync” state,
repeat steps 2 and 3 above.
In Fibre Channel and Gigabit Ethernet applications,
multiple consecutive K28.5 characters cannot be gen-
erated. However, for serial backplane applications this
can occur. The S2004 must be able to operate prop-
erly when multiple K28.5 characters are received.
After the first K28.5 is detected and aligned, the RCxP/
N clock will operate without glitches or loss of cycles.
Receiver Output Clocking
8B/10B Decoding
The S2004 parallel output clock source is deter-mined
by the TMODE selection. When REFCLK clocking is
selected (TMODE = Low), the parallel output clocks
(RCxP/N) are sourced from the TCLKA input. When
TCLK clocking is selected (External Clocking Mode),
the parallel output clocks are derived from the recov-
ered clock from each channel. Table 9 describes the
receiver output clocking options available.
After serial to parallel conversion, the S2004 provides
8B/10B decoding of the data. The received 10-bit code
word is decoded to recover the original 8-bit data. The
decoder also checks for errors and flags, either invalid
code word errors or running disparity errors by asser-
tion of the ERRx signal. Error type is determined by
examining the EOF output in accordance with Table 7.
When more than one reportable condition occurs
simultaneously, reporting is in accordance with the
rank assigned by Table 7.
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